hhd70: started refactoring of cc1101 code

5 files changed, 436 insertions, 400 deletions

diff --git a/software/avr.lib/cc1101_defines.h b/software/avr.lib/cc1101_defines.h
new file mode 100644
index 0000000..e9e2e67
--- /dev/null
+++ b/software/avr.lib/cc1101_defines.h
@@ -0,0 +1,153 @@
+/*
+ *  spreadspace avr utils
+ *
+ *
+ *  Copyright (C) 2013-2015 Christian Pointner <equinox@spreadspace.org>
+ *
+ *  This file is part of spreadspace avr utils.
+ *
+ *  spreadspace avr utils is free software: you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation, either version 3 of the License, or
+ *  any later version.
+ *
+ *  spreadspace avr utils is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with spreadspace avr utils. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef SPREADAVR_CC1101_defines_h_INCLUDED
+#define SPREADAVR_CC1101_defines_h_INCLUDED
+
+//// header byte
+#define CC1101_HEADER_READ           0x80
+#define CC1101_HEADER_WRITE          0x00
+#define CC1101_HEADER_BURST          0x40
+#define CC1101_HEADER_READONLY       0xC0
+#define CC1101_HEADER_COMMAND        0x00
+
+//read/write config registers:
+#define CC1101_REG_RW_IOCFG2         0x00
+#define CC1101_REG_RW_IOCFG1         0x01
+#define CC1101_REG_RW_IOCFG0         0x02
+#define CC1101_REG_RW_FIFOTHR        0x03
+#define CC1101_REG_RW_SYNC1          0x04
+#define CC1101_REG_RW_SYNC0          0x05
+#define CC1101_REG_RW_PKTLEN         0x06
+#define CC1101_REG_RW_PKTCTRL1       0x07
+#define CC1101_REG_RW_PKTCTRL0       0x08
+#define CC1101_REG_RW_ADDR           0x09
+#define CC1101_REG_RW_CHANNR         0x0A
+#define CC1101_REG_RW_FSCTRL1        0x0B
+#define CC1101_REG_RW_FSCTRL0        0x0C
+#define CC1101_REG_RW_FREQ2          0x0D
+#define CC1101_REG_RW_FREQ1          0x0E
+#define CC1101_REG_RW_FREQ0          0x0F
+#define CC1101_REG_RW_MDMCFG4        0x10
+#define CC1101_REG_RW_MDMCFG3        0x11
+#define CC1101_REG_RW_MDMCFG2        0x12
+#define CC1101_REG_RW_MDMCFG1        0x13
+#define CC1101_REG_RW_MDMCFG0        0x14
+#define CC1101_REG_RW_DEVIATN        0x15
+#define CC1101_REG_RW_MCSM2          0x16
+#define CC1101_REG_RW_MCSM1          0x17
+#define CC1101_REG_RW_MCSM0          0x18
+#define CC1101_REG_RW_FOCCFG         0x19
+#define CC1101_REG_RW_BSCFG          0x1A
+#define CC1101_REG_RW_AGCCTRL2       0x1B
+#define CC1101_REG_RW_AGCCTRL1       0x1C
+#define CC1101_REG_RW_AGCCTRL0       0x1D
+#define CC1101_REG_RW_WOREVT1        0x1E
+#define CC1101_REG_RW_WOREVT0        0x1F
+#define CC1101_REG_RW_WORCTRL        0x20
+#define CC1101_REG_RW_FREND1         0x21
+#define CC1101_REG_RW_FREND0         0x22
+#define CC1101_REG_RW_FSCAL3         0x23
+#define CC1101_REG_RW_FSCAL2         0x24
+#define CC1101_REG_RW_FSCAL1         0x25
+#define CC1101_REG_RW_FSCAL0         0x26
+#define CC1101_REG_RW_RCCTRL1        0x27
+#define CC1101_REG_RW_RCCTRL0        0x28
+#define CC1101_REG_RW_FSTEST         0x29
+#define CC1101_REG_RW_PTEST          0x2A
+#define CC1101_REG_RW_AGCTEST        0x2B
+#define CC1101_REG_RW_TEST2          0x2C
+#define CC1101_REG_RW_TEST1          0x2D
+#define CC1101_REG_RW_TEST0          0x2E
+
+#define CC1101_REG_RW_MAX            0x2E
+
+//read-only status registers:
+#define CC1101_REG_RO_PARTNUM        0x30
+#define CC1101_REG_RO_VERSION        0x31
+#define CC1101_REG_RO_FREQUEST       0x32
+#define CC1101_REG_RO_LQI            0x33
+#define CC1101_REG_RO_RSSI           0x34
+#define CC1101_REG_RO_MARCSTATE      0x35
+#define CC1101_REG_RO_WORTIME1       0x36
+#define CC1101_REG_RO_WORTIME0       0x37
+#define CC1101_REG_RO_PKTSTATUS      0x38
+#define CC1101_REG_RO_VCO_VC_DAC     0x39
+#define CC1101_REG_RO_TXBYTES        0x3A
+#define CC1101_REG_RO_RXBYTES        0x3B
+#define CC1101_REG_RO_RCCTRL1_STATUS 0x3C
+#define CC1101_REG_RO_RCCTRL0_STATUS 0x3D
+
+#define CC1101_REG_RO_MIN            0x30
+#define CC1101_REG_RO_MAX            0x3D
+
+//commands:
+#define CC1101_CMD_SRES              0x30
+#define CC1101_CMD_SFSTXON           0x31
+#define CC1101_CMD_SXOFF             0x32
+#define CC1101_CMD_SCAL              0x33
+#define CC1101_CMD_SRX               0x34
+#define CC1101_CMD_STX               0x35
+#define CC1101_CMD_SIDLE             0x36
+#define CC1101_CMD_SWOR              0x38
+#define CC1101_CMD_SPWD              0x39
+#define CC1101_CMD_SFRX              0x3A
+#define CC1101_CMD_SFTX              0x3B
+#define CC1101_CMD_SWORRST           0x3C
+#define CC1101_CMD_SNOP              0x3D
+
+#define CC1101_CMD_MIN               0x30
+#define CC1101_CMD_MAX               0x3D
+
+//power amplifier table
+#define CC1101_REG_PATABLE           0x3E
+//data FIFOs
+#define CC1101_REG_FIFO              0x3F
+
+
+#define CC1101_ADDR_MAX              0x3F
+
+
+
+////status byte:
+#define CC1101_STATUS_CHIP_NOT_RDY(x)          (x & 0b10000000)
+#define CC1101_STATUS_IDLE(x)                 ((x & 0b01110000) == 0b00000000)
+#define CC1101_STATUS_RXMODE(x)               ((x & 0b01110000) == 0b00010000)
+#define CC1101_STATUS_TXMODE(x)               ((x & 0b01110000) == 0b00100000)
+#define CC1101_STATUS_FSTXON(x)               ((x & 0b01110000) == 0b00110000)
+#define CC1101_STATUS_CALIBRATE(x)            ((x & 0b01110000) == 0b01000000)
+#define CC1101_STATUS_SETTLING(x)             ((x & 0b01110000) == 0b01010000)
+#define CC1101_STATUS_RXFIFO_OVERFLOW(x)      ((x & 0b01110000) == 0b01100000)
+#define CC1101_STATUS_TXFIFO_OVERFLOW(x)      ((x & 0b01110000) == 0b01110000)
+#define CC1101_STATUS_FIFO_BYTES_AVAILABLE(x)  (x & 0b00001111)
+
+
+#define CC1101_FIFO_MAX_LEN    64
+
+//freq    Fosc/65536
+#ifdef CC1101_QUARTZ_26M
+#define CC1101_FREQ_CORR 396.728515 // = 26000000/65536
+#else
+#error Please set Quartz Frequency using the variable: CC1101_QUARTZ_*
+#endif // CC1101_QUARTZ_26M
+
+#endif
diff --git a/software/hhd70dongle/Makefile b/software/hhd70dongle/Makefile
index 1fea29b..fe926c2 100644
--- a/software/hhd70dongle/Makefile
+++ b/software/hhd70dongle/Makefile
@@ -45,6 +45,8 @@ LUFA_COMPONENTS := USB USBCLASS
 
 include ../avr.include.mk
 
+CFLAGS += -D CC1101_QUARTZ_26M
+
 program0: RESET_PARAM:=/dev/ttyACM0
 program0: program
 
diff --git a/software/hhd70dongle/c1101lib.c b/software/hhd70dongle/c1101lib.c
index c24c398..209ccee 100644
--- a/software/hhd70dongle/c1101lib.c
+++ b/software/hhd70dongle/c1101lib.c
@@ -31,198 +31,178 @@
  *
  */
 #include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
 #include <avr/io.h>
 #include <util/delay.h>
 
 #include "c1101lib.h"
+#include "cc1101_defines.h"
 #include "hhd70.h"
 #include "util.h"
 
-/**** Helper Functions ****/
+// internal functions
 
-#define SPIC1101_MAX_WAIT 21
+#define CC1101_MAX_WAIT_RDY 21
 
-
-
-/* ######          ######
-             LUFA Library
-     Copyright (C) Dean Camera, 2012.
-
-  dean [at] fourwalledcubicle [dot] com
-           www.lufa-lib.org
-*/
-//#include <LUFA/Drivers/Misc/RingBuffer.h>
-#include <LUFA/Drivers/USB/USB.h>
-
-   /* Global I/O Buffers: */
-//static RingBuffer_t SPItoUSB_Buffer;
-//static uint8_t      SPItoUSB_Buffer_Data[8];
-
-
-int16_t c1101_spi_write_byte_ok_get_status(char data)
+static int16_t c1101_spi_write_byte_ok_get_status(uint8_t data)
 {
-    //~ uint8_t debug_sb[6];
-    char sb;
-    unsigned int attempts = 0;
-    do
-    {
-        sb = hhd70_spi_exchange_byte(data);
+  uint8_t sb;
+  unsigned int attempts = 0;
+  do
+  {
+    sb = hhd70_spi_exchange_byte(data);
         //Note: content of returned StatusByte is actually context depenedant on sent command
         //            i.e. we won't get Fifo Byte count or overflow status on normal command and so on
         //            e.g. we only get TX Fifo Free Byte count while writing to TX Fifo
         //            thus it makes sense to only check for CHIP_RDY here
-        //~ ((uint8_t*)"spi byte exchanged ",255);
-        //~ debug_sprint_int16hex(debug_sb, sb);
-        //~ (debug_sb,255);
-        if (attempts++ > SPIC1101_MAX_WAIT)
-            return -1;
-    } while ( SPIC1101_SB_CHIP_NOT_RDY(sb) );
-    return sb;
+    if (attempts++ > CC1101_MAX_WAIT_RDY)
+      return -1;
+  } while (CC1101_STATUS_CHIP_NOT_RDY(sb));
+  return sb;
 }
 
-int16_t c1101_spi_strobe_command(char address)
+int16_t c1101_spi_strobe_command(uint8_t cmd)
 {
-    char rbyte;
-    if (address < 0x30)
-        return -1;
-    hhd70_spi_cs_enable();
-    hhd70_c1101_wait_chip_rdy();
-    //POST DEBUG: don't return anything
-    rbyte = c1101_spi_write_byte_ok_get_status(address);
-    if (rbyte < 0)
-        return -1;
-    hhd70_spi_cs_disable();
-    return rbyte;
+  if(cmd < CC1101_CMD_MIN || cmd > CC1101_CMD_MAX)
+    return -1;
+
+  hhd70_spi_cs_enable();
+  hhd70_c1101_wait_chip_rdy();
+  uint8_t rbyte = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_COMMAND | cmd);
+  if(rbyte < 0)
+    return -1;
+  hhd70_spi_cs_disable();
+  return rbyte;
 }
 
-// note addresses range from 0x00 to 0x2F for normal registers and 0xF0 to 0xFD for special status registers
-int16_t c1101_spi_read_register(char address)
+int16_t c1101_spi_read_register(uint8_t addr)
 {
-    char rbyte;
-    if (address < 0x30)
-        address |= 0x80;
-    else
-        address |= 0xC0;
-    hhd70_spi_cs_enable();
-    hhd70_c1101_wait_chip_rdy();
-    if (c1101_spi_write_byte_ok_get_status(address) < 0)
-        return -1;
-    rbyte = hhd70_spi_read_byte();
-    hhd70_spi_cs_disable();
-    return rbyte;
+  if(addr > CC1101_ADDR_MAX)
+    return -1;
+
+  if(addr > CC1101_REG_RW_MAX)
+    addr |= CC1101_HEADER_READONLY;
+  else
+    addr |= CC1101_HEADER_READ;
+
+  hhd70_spi_cs_enable();
+  hhd70_c1101_wait_chip_rdy();
+  if(c1101_spi_write_byte_ok_get_status(addr) < 0)
+    return -1;
+  uint8_t rbyte = hhd70_spi_read_byte();
+  hhd70_spi_cs_disable();
+  return rbyte;
 }
 
-// note addresses range from 0x00 to 0x2F for normal registers
-int16_t c1101_spi_write_register(char address, char byte)
+int16_t c1101_spi_write_register(uint8_t addr, uint8_t byte)
 {
-    hhd70_spi_cs_enable();
-    hhd70_c1101_wait_chip_rdy();
-    if (c1101_spi_write_byte_ok_get_status(address & 0x3F) < 0)
-        return -1;
-    _delay_ms(2);
-    if (c1101_spi_write_byte_ok_get_status(byte) < 0)
-        return -1;
-    hhd70_spi_cs_disable();
-    return 1;
+  if(addr > CC1101_REG_RW_MAX)
+    return -1;
+
+  hhd70_spi_cs_enable();
+  hhd70_c1101_wait_chip_rdy();
+  if(c1101_spi_write_byte_ok_get_status(CC1101_HEADER_WRITE | addr) < 0)
+    return -1;
+  _delay_ms(2); // TODO: why wait here???
+  if(c1101_spi_write_byte_ok_get_status(byte) < 0)
+    return -1;
+  hhd70_spi_cs_disable();
+  return 1;
 }
 
-void c1101_spi_dump_registers_to_usb(void)
+void c1101_spi_dump_registers(void)
 {
-    int c = 0;
-    char debug_sb[6];
-    hhd70_spi_cs_enable();
-    hhd70_c1101_wait_chip_rdy();
-    if (c1101_spi_write_byte_ok_get_status(0xC0) < 0)
-        return;
-    printf("dump all 46 registers:\r\n");
-    for (c=0; c<47; c++)
-    {
-        debug_sprint_int16hex(debug_sb, hhd70_spi_read_byte());
-        printf("%s", debug_sb);
-        printf("\r\n");
-    }
-    hhd70_spi_cs_disable();
+  int c = 0;
+  char debug_sb[6];
+  hhd70_spi_cs_enable();
+  hhd70_c1101_wait_chip_rdy();
+  if (c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | 0x00) < 0)
+    return;
+  printf("dump all 46 registers:\r\n");
+  for (c = 0; c < CC1101_REG_RW_MAX; c++) {
+    debug_sprint_int16hex(debug_sb, hhd70_spi_read_byte());
+    printf("%s", debug_sb);
+    printf("\r\n");
+  }
+  hhd70_spi_cs_disable();
 }
 
-int c1101_spi_read_rxfifo(int leave_num_bytes, char *buffer, int maxlen)
+int c1101_spi_read_rxfifo(int leave_num_bytes, uint8_t *buffer, int maxlen)
 {
-    int num_read = 0;
-    uint8_t num_available = 0;
-    hhd70_spi_cs_enable();
-    hhd70_c1101_wait_chip_rdy();
-    if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_RXBYTES) < 0)
-        return -1;
-    num_available = hhd70_spi_read_byte();
-    if (num_available == 0)
-        return 0;
-    if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST) < 0)
-        return -1;
-    while (maxlen--  > 0 && num_available - num_read > leave_num_bytes)
-    {
-        buffer[num_read++] = hhd70_spi_read_byte();
-    }
-    hhd70_spi_cs_disable();
-    return num_read;
+  int num_read = 0;
+  uint8_t num_available = 0;
+  hhd70_spi_cs_enable();
+  hhd70_c1101_wait_chip_rdy();
+  if (c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READONLY | CC1101_REG_RO_RXBYTES) < 0)
+    return -1;
+
+  num_available = hhd70_spi_read_byte();
+  if (num_available == 0)
+    return 0;
+  if (c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | CC1101_REG_FIFO) < 0)
+    return -1;
+  while (maxlen--  > 0 && num_available - num_read > leave_num_bytes)
+    buffer[num_read++] = hhd70_spi_read_byte();
+
+  hhd70_spi_cs_disable();
+  return num_read;
 }
 
 //note: currently this function reads at most 15 bytes
-int c1101_spi_read_rxfifo_max15(int leave_num_bytes, char *buffer, int maxlen)
-{
-    int16_t sb;
-    int num_read = 0;
-    hhd70_spi_cs_enable();
-    hhd70_c1101_wait_chip_rdy();
-    sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST);
-    if (sb < 0)
-        return -1;
-    //note if SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb)  == 15 then 15 or more bytes are available
-    while (maxlen--  > 0 && SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) - num_read > leave_num_bytes)
-    {
+int c1101_spi_read_rxfifo_max15(int leave_num_bytes, uint8_t *buffer, int maxlen)
+{
+  int16_t sb;
+  int num_read = 0;
+  hhd70_spi_cs_enable();
+  hhd70_c1101_wait_chip_rdy();
+  sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | CC1101_REG_FIFO);
+  if (sb < 0)
+    return -1;
+      //note if CC1101_STATUS_FIFO_BYTES_AVAILABLE(sb)  == 15 then 15 or more bytes are available
+  while (maxlen--  > 0 && CC1101_STATUS_FIFO_BYTES_AVAILABLE(sb) - num_read > leave_num_bytes) {
         //hope this works !!
-        buffer[num_read++] = hhd70_spi_read_byte();
-    }
-    hhd70_spi_cs_disable();
-    return num_read;
+    buffer[num_read++] = hhd70_spi_read_byte();
+  }
+  hhd70_spi_cs_disable();
+  return num_read;
 }
 
 //note: always check if num_written returned == len given
-int c1101_spi_write_txfifo(char *buffer, int len)
-{
-    char sb;
-    int num_written = 0;
-    hhd70_spi_cs_enable();
-    hhd70_c1101_wait_chip_rdy();
-    sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_WRITE_BURST);
-    if (sb < 0)
-        return -1;
-    while (len-- > 0 && SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) > 2)
-    {
-        sb = c1101_spi_write_byte_ok_get_status(buffer[num_written++]);
-    }
-    hhd70_spi_cs_disable();
-    return num_written;
-}
-
-//patable muste be char array of length 8
+int c1101_spi_write_txfifo(uint8_t *buffer, int len)
+{
+  uint8_t sb;
+  int num_written = 0;
+  hhd70_spi_cs_enable();
+  hhd70_c1101_wait_chip_rdy();
+  sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | CC1101_REG_FIFO);
+  if (sb < 0)
+    return -1;
+  while (len-- > 0 && CC1101_STATUS_FIFO_BYTES_AVAILABLE(sb) > 2) {
+    sb = c1101_spi_write_byte_ok_get_status(buffer[num_written++]);
+  }
+  hhd70_spi_cs_disable();
+  return num_written;
+}
+
+//patable muste be uint8_t array of length 8
 int c1101_spi_write_patable(uint8_t const patable[])
 {
-    int16_t sb;
-    int8_t len = 8;
-    hhd70_spi_cs_enable();
-    hhd70_c1101_wait_chip_rdy();
-    sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_PATABLE_WRITE_BURST);
-    if (sb < 0)
-        return -1;
-    while (len-- > 0)
-    {
-        sb = c1101_spi_write_byte_ok_get_status(*patable);
-        patable++;
-    }
-    hhd70_spi_cs_disable();
-    return sb;
+  int16_t sb;
+  int8_t len = 8;
+  hhd70_spi_cs_enable();
+  hhd70_c1101_wait_chip_rdy();
+  sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_WRITE | CC1101_HEADER_BURST | CC1101_REG_PATABLE);
+  if (sb < 0)
+    return -1;
+  while (len-- > 0) {
+    sb = c1101_spi_write_byte_ok_get_status(*patable);
+    patable++;
+  }
+  hhd70_spi_cs_disable();
+  return sb;
 }
 
-
 static uint8_t const pa_table_values_[] = { 0x00, 0x30, 0x20, 0x10, 0x01, 0x02, 0x11, 0x03,
                     0x12, 0x04, 0x05, 0x13, 0x06, 0x07, 0x21, 0x14, 0x08, 0x09, 0x0A, 0x15,
                     0x0B, 0x31, 0x16, 0x0C, 0x0D, 0x0E, 0x17, 0x0F, 0x22, 0x18, 0x19, 0x1A,
@@ -238,69 +218,70 @@ static uint8_t const pa_table_values_[] = { 0x00, 0x30, 0x20, 0x10, 0x01, 0x02,
 #define PA_TABLE_VALUES_MAX ((sizeof(pa_table_values_)/sizeof(uint8_t))-1)
 static uint8_t ook_power_ = 83; // ==> 3F
 
+
 /**** External Functions ****/
 
 uint16_t c1101_setFSKDeviationFromCarrier(int8_t m, int8_t e)
 {
-    c1101_spi_write_register(SPIC1101_ADDR_DEVIATN, (m & 0x7) | ((e & 0x7) << 4));
+    c1101_spi_write_register(CC1101_REG_RW_DEVIATN, (m & 0x7) | ((e & 0x7) << 4));
     return (1983u * (8u+((uint32_t)m)) * (1u << ((uint32_t)e))) / 100; //return +- deviation in 10Hz Steps
 }
 
 void c1101_init(void)
 {
     //reset C1101
-    c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
+    c1101_spi_strobe_command(CC1101_CMD_SRES);
     _delay_ms(100);
     //flush FIFOs
-    c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
-    c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
-    //dump pre-init default values to usb
-    c1101_spi_dump_registers_to_usb();
+    c1101_spi_strobe_command(CC1101_CMD_SFRX);
+    c1101_spi_strobe_command(CC1101_CMD_SFTX);
+    //dump pre-init default values to stdout
+    c1101_spi_dump_registers();
     //enable analog temperature sensor on GDO0
-    c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x80);
+    c1101_spi_write_register(CC1101_REG_RW_IOCFG0, 0x80);
     //enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO)
-    c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
+    c1101_spi_write_register(CC1101_REG_RW_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
     // FIFOTHR       RX FIFO and TX FIFO Thresholds
     // pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx)
-    //c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 2); //assert at 12 bytes in RX Fifo and 53 in TX Fifo
-    c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 0);  //assert at 4 bytes in RX Fifo and 61 in TX Fifo
+    //c1101_spi_write_register(CC1101_REG_RW_FIFOTHR, 2); //assert at 12 bytes in RX Fifo and 53 in TX Fifo
+    c1101_spi_write_register(CC1101_REG_RW_FIFOTHR, 0);  //assert at 4 bytes in RX Fifo and 61 in TX Fifo
     // PKTCTRL0      Packet Automation Control
-    //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode
-    c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
-    //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000101); //crc enabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
-    c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet
+    //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode
+    c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+    //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000101); //crc enabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+    c1101_spi_write_register(CC1101_REG_RW_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet
     // FSCTRL1       Frequency Synthesizer Control
-    c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, 0x06);
+    c1101_spi_write_register(CC1101_REG_RW_FSCTRL1, 0x06);
     // FREQn         Frequency Control Words
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ2, 0x10); //should be 435.125 mhz
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ1, 0xBF);
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ0, 0xEF);
-    c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, 0); //frequency offset
+    c1101_spi_write_register(CC1101_REG_RW_FREQ2, 0x10); //should be 435.125 mhz
+    c1101_spi_write_register(CC1101_REG_RW_FREQ1, 0xBF);
+    c1101_spi_write_register(CC1101_REG_RW_FREQ0, 0xEF);
+    c1101_spi_write_register(CC1101_REG_RW_FSCTRL0, 0); //frequency offset
     // MDMCFGn       Modem Configuration
-    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4, 0xF8);
-    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3, 0x83);
-    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2, 0x12); //gfsk, 15/16 sync word
-    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG1, 0x00);
+    c1101_spi_write_register(CC1101_REG_RW_MDMCFG4, 0xF8);
+    c1101_spi_write_register(CC1101_REG_RW_MDMCFG3, 0x83);
+    c1101_spi_write_register(CC1101_REG_RW_MDMCFG2, 0x12); //gfsk, 15/16 sync word
+    c1101_spi_write_register(CC1101_REG_RW_MDMCFG1, 0x00);
     //Sync Word
-    c1101_spi_write_register(SPIC1101_ADDR_SYNC1, 0x21);
-    c1101_spi_write_register(SPIC1101_ADDR_SYNC0, 0x42);
+    c1101_spi_write_register(CC1101_REG_RW_SYNC1, 0x21);
+    c1101_spi_write_register(CC1101_REG_RW_SYNC0, 0x42);
     // DEVIATN       Modem Deviation Setting
-    c1101_spi_write_register(SPIC1101_ADDR_DEVIATN, 0x11); //0x11 equals deviation of 3.5kHz; 0x27 equals deviation of 11.9kHz
+    c1101_spi_write_register(CC1101_REG_RW_DEVIATN, 0x11); //0x11 equals deviation of 3.5kHz; 0x27 equals deviation of 11.9kHz
     // MCSM0         Main Radio Control State Machine Configuration
-    c1101_spi_write_register(SPIC1101_ADDR_MCSM0, 0x18);
-    c1101_spi_write_register(SPIC1101_ADDR_MCSM1, 0b00111100);  // State RX after recieving packet->  stay in RX; State TX after sending packet -> IDLE
+    c1101_spi_write_register(CC1101_REG_RW_MCSM0, 0x18);
+    c1101_spi_write_register(CC1101_REG_RW_MCSM1, 0b00111100);  // State RX after recieving packet->  stay in RX; State TX after sending packet -> IDLE
     // FOCCFG        Frequency Offset Compensation Configuration
-    c1101_spi_write_register(SPIC1101_ADDR_FOCCFG, 0x16);
+    c1101_spi_write_register(CC1101_REG_RW_FOCCFG, 0x16);
     // WORCTRL       Wake On Radio Control
-    c1101_spi_write_register(SPIC1101_ADDR_WORCTRL, 0xFB);
+    c1101_spi_write_register(CC1101_REG_RW_WORCTRL, 0xFB);
     // FSCALn        Frequency Synthesizer Calibration
-    c1101_spi_write_register(SPIC1101_ADDR_FSCAL3, 0xE9);
-    c1101_spi_write_register(SPIC1101_ADDR_FSCAL2, 0x2A);
-    c1101_spi_write_register(SPIC1101_ADDR_FSCAL1, 0x00);
-    c1101_spi_write_register(SPIC1101_ADDR_FSCAL0, 0x1F);
+    c1101_spi_write_register(CC1101_REG_RW_FSCAL3, 0xE9);
+    c1101_spi_write_register(CC1101_REG_RW_FSCAL2, 0x2A);
+    c1101_spi_write_register(CC1101_REG_RW_FSCAL1, 0x00);
+    c1101_spi_write_register(CC1101_REG_RW_FSCAL0, 0x1F);
     //FREN0  TX Power:
-    c1101_spi_write_register(SPIC1101_ADDR_FREND0, 0x10);  //should be set using RF-Studio !!, for now, only use PA-Table Entry[0] no power ramping !! (FIXME: but should maybe be used)
-    c1101_spi_write_register(SPIC1101_ADDR_PATABLE_WRITE, 0xC0);  //write PATABLE[0] only, rest needs to be written in Burst-Mode !  set to max power 10dBm
+    c1101_spi_write_register(CC1101_REG_RW_FREND0, 0x10);  //should be set using RF-Studio !!, for now, only use PA-Table Entry[0] no power ramping !! (FIXME: but should maybe be used)
+    c1101_spi_write_register(CC1101_REG_PATABLE, 0xC0);  //write PATABLE[0] only, rest needs to be written in Burst-Mode !  set to max power 10dBm
 
     // note: for now: assume f_xosc to be 26 Mhz
     // for ~433.125 Mhz -> freq = 1091741, freq_offset = 0
@@ -341,15 +322,15 @@ void c1101_init_w_rfstudiosettings1(void)
     // Rf settings for CC1101
     //
     //reset C1101
-    c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
+    c1101_spi_strobe_command(CC1101_CMD_SRES);
     _delay_ms(100);
     //flush FIFOs
-    c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
-    c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
+    c1101_spi_strobe_command(CC1101_CMD_SFRX);
+    c1101_spi_strobe_command(CC1101_CMD_SFTX);
     //enable analog temperature sensor on GDO0
-    c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x80);
+    c1101_spi_write_register(CC1101_REG_RW_IOCFG0, 0x80);
     //enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO)
-    c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
+    c1101_spi_write_register(CC1101_REG_RW_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
 
     //Values from SmartRFStudio:
     c1101_spi_write_patable(pa_table);
@@ -382,41 +363,41 @@ void c1101_init_ook_beacon(void)
     //  PA table by TI
 
     //reset C1101
-    c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
+    c1101_spi_strobe_command(CC1101_CMD_SRES);
     _delay_ms(100);
     //flush FIFOs
-    c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
-    c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
+    c1101_spi_strobe_command(CC1101_CMD_SFRX);
+    c1101_spi_strobe_command(CC1101_CMD_SFTX);
 
     //
     // Rf settings for CC1101
     //
-    c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x00);
+    c1101_spi_write_register(CC1101_REG_RW_IOCFG0, 0x00);
     //enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO)
-    c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
+    c1101_spi_write_register(CC1101_REG_RW_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
     // pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx)
-    //c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
-    c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 0);  //assert at 4 bytes in RX Fifo and 61 in TX Fifo
-    //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0,0x12);//Packet Automation Control
-    //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
-    c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000110001); //crc disabled; asynchronous serial input on GDO0
-    c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1,0x06); //Frequency Synthesizer Control
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ2,0x10);   //Frequency Control Word, High Byte
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ1,0xD3);   //Frequency Control Word, Middle Byte
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ0,0xF0);   //Frequency Control Word, Low Byte
-    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4,0xF5); //Modem Configuration
-    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3,0x43); //Modem Configuration
-    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2,0x30); //Modem Configuration
-    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG1,0x00); //Modem Configuration
-    c1101_spi_write_register(SPIC1101_ADDR_DEVIATN,0x07); //Modem Deviation Setting
-    c1101_spi_write_register(SPIC1101_ADDR_MCSM0,0x18);   //Main Radio Control State Machine Configuration
-    c1101_spi_write_register(SPIC1101_ADDR_FOCCFG,0x16);  //Frequency Offset Compensation Configuration
-    c1101_spi_write_register(SPIC1101_ADDR_WORCTRL,0xFB); //Wake On Radio Control
-    c1101_spi_write_register(SPIC1101_ADDR_FREND0,0x11);  //Front End TX Configuration // PA_POWER[2:0] = 1
-    c1101_spi_write_register(SPIC1101_ADDR_FSCAL3,0xE9);  //Frequency Synthesizer Calibration
-    c1101_spi_write_register(SPIC1101_ADDR_FSCAL2,0x2A);  //Frequency Synthesizer Calibration
-    c1101_spi_write_register(SPIC1101_ADDR_FSCAL1,0x00);  //Frequency Synthesizer Calibration
-    c1101_spi_write_register(SPIC1101_ADDR_FSCAL0,0x1F);  //Frequency Synthesizer Calibration
+    //c1101_spi_write_register(CC1101_REG_RW_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
+    c1101_spi_write_register(CC1101_REG_RW_FIFOTHR, 0);  //assert at 4 bytes in RX Fifo and 61 in TX Fifo
+    //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0,0x12);//Packet Automation Control
+    //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+    c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000110001); //crc disabled; asynchronous serial input on GDO0
+    c1101_spi_write_register(CC1101_REG_RW_FSCTRL1,0x06); //Frequency Synthesizer Control
+    c1101_spi_write_register(CC1101_REG_RW_FREQ2,0x10);   //Frequency Control Word, High Byte
+    c1101_spi_write_register(CC1101_REG_RW_FREQ1,0xD3);   //Frequency Control Word, Middle Byte
+    c1101_spi_write_register(CC1101_REG_RW_FREQ0,0xF0);   //Frequency Control Word, Low Byte
+    c1101_spi_write_register(CC1101_REG_RW_MDMCFG4,0xF5); //Modem Configuration
+    c1101_spi_write_register(CC1101_REG_RW_MDMCFG3,0x43); //Modem Configuration
+    c1101_spi_write_register(CC1101_REG_RW_MDMCFG2,0x30); //Modem Configuration
+    c1101_spi_write_register(CC1101_REG_RW_MDMCFG1,0x00); //Modem Configuration
+    c1101_spi_write_register(CC1101_REG_RW_DEVIATN,0x07); //Modem Deviation Setting
+    c1101_spi_write_register(CC1101_REG_RW_MCSM0,0x18);   //Main Radio Control State Machine Configuration
+    c1101_spi_write_register(CC1101_REG_RW_FOCCFG,0x16);  //Frequency Offset Compensation Configuration
+    c1101_spi_write_register(CC1101_REG_RW_WORCTRL,0xFB); //Wake On Radio Control
+    c1101_spi_write_register(CC1101_REG_RW_FREND0,0x11);  //Front End TX Configuration // PA_POWER[2:0] = 1
+    c1101_spi_write_register(CC1101_REG_RW_FSCAL3,0xE9);  //Frequency Synthesizer Calibration
+    c1101_spi_write_register(CC1101_REG_RW_FSCAL2,0x2A);  //Frequency Synthesizer Calibration
+    c1101_spi_write_register(CC1101_REG_RW_FSCAL1,0x00);  //Frequency Synthesizer Calibration
+    c1101_spi_write_register(CC1101_REG_RW_FSCAL0,0x1F);  //Frequency Synthesizer Calibration
 
     c1101_ook_power_set(ook_power_);
     hhd70_config_GDO0_OOK_output(true);
@@ -459,81 +440,81 @@ void c1101_ook_power_dec()
 void c1101_permanently_save_current_rx_tx_freqoffset_auto_compensation()
 {
     int16_t freq_offset;
-    freq_offset = c1101_spi_read_register(SPIC1101_ADDR_FREQUEST);
+    freq_offset = c1101_spi_read_register(CC1101_REG_RO_FREQUEST);
     if (freq_offset >= 0)
     {
-        c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, (uint8_t) freq_offset);
+        c1101_spi_write_register(CC1101_REG_RW_FSCTRL0, (uint8_t) freq_offset);
     }
 }
 
 // WARNING: All content of the PATABLE except for the first byte (index 0) is lost when entering the SLEEP state.
-char c1101_putToSleep(void)
+uint8_t c1101_putToSleep(void)
 {
-    return c1101_spi_strobe_command(SPIC1101_ADDR_SPWD);
+    return c1101_spi_strobe_command(CC1101_CMD_SPWD);
 }
 
 uint16_t c1101_measureTemp(void)
 {
     uint16_t temp;
-    char ptest_value=0x7F;
-    ptest_value = c1101_spi_read_register(SPIC1101_ADDR_PTEST);
-    c1101_spi_write_register(SPIC1101_ADDR_PTEST, 0xBF);
+    uint8_t ptest_value=0x7F;
+    ptest_value = c1101_spi_read_register(CC1101_REG_RW_PTEST);
+    c1101_spi_write_register(CC1101_REG_RW_PTEST, 0xBF);
     _delay_ms(5);
     temp = adc_read(ADCMUX_INTERNALTEMP);
-    c1101_spi_write_register(SPIC1101_ADDR_PTEST, ptest_value);
+    c1101_spi_write_register(CC1101_REG_RW_PTEST, ptest_value);
     return temp;
 }
 
-void c1101_handleMARCStatusByte(char sb)
+void c1101_handleMARCStatusByte(uint8_t sb)
 {
     //on RXFifo Overflow, Flush RX Fifo
     if (sb == 0x11)
     {
-        c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
+        c1101_spi_strobe_command(CC1101_CMD_SFRX);
         printf("RX fifo flushed\r\n");
     }
     //on TXFifo Overflow, Flush TX Fifo
     else if (sb == 0x16)
     {
-        c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
+        c1101_spi_strobe_command(CC1101_CMD_SFTX);
         printf("TX fifo flushed\r\n");
     }
 }
 
-void c1101_handleStatusByte(char sb)
+void c1101_handleStatusByte(uint8_t sb)
 {
     //on RXFifo Overflow, Flush RX Fifo
-    if (SPIC1101_SB_RXFIFO_OVERFLOW(sb))
+    if (CC1101_STATUS_RXFIFO_OVERFLOW(sb))
     {
-        c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
+        c1101_spi_strobe_command(CC1101_CMD_SFRX);
         printf("RX fifo flushed\r\n");
     }
     //on TXFifo Overflow, Flush TX Fifo
-    if (SPIC1101_SB_TXFIFO_OVERFLOW(sb))
+    if (CC1101_STATUS_TXFIFO_OVERFLOW(sb))
     {
-        c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
+        c1101_spi_strobe_command(CC1101_CMD_SFTX);
         printf("TX fifo flushed\r\n");
     }
 }
 
-char c1101_getStatus(void)
+uint8_t c1101_getStatus(void)
 {
-    char sb=0;
+    uint8_t sb=0;
     hhd70_spi_cs_enable();
     hhd70_c1101_wait_chip_rdy();
-    sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_SNOP);
+    sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_COMMAND | CC1101_CMD_SNOP);
     hhd70_spi_cs_disable();
     c1101_handleStatusByte(sb);
     return sb;
 }
 
-char c1101_getMARCState(void)
+uint8_t c1101_getMARCState(void)
 {
-    char sb=0;
-    sb = c1101_spi_read_register(SPIC1101_ADDR_MARCSTATE);
+    uint8_t sb=0;
+    sb = c1101_spi_read_register(CC1101_REG_RO_MARCSTATE);
     sb &= 0x1F;
     //debug start
-    /* char debug_sb[6]; */
+    /* uint8_t debug_sb[6]; */
     /* printf("c1101 MARCState:\r\n"); */
     /* debug_sprint_int16hex(debug_sb, sb); */
     /* printf("%s", debug_sb); */
@@ -544,7 +525,7 @@ char c1101_getMARCState(void)
 
 uint8_t c1101_getNumBytesInTXFifo(void)
 {
-    return c1101_spi_read_register(SPIC1101_ADDR_TXBYTES);
+    return c1101_spi_read_register(CC1101_REG_RO_TXBYTES);
 }
 
 
@@ -555,7 +536,7 @@ bool c1101_waitUntilIDLEState(uint16_t timeout_ms)
     for (uint16_t c = 0; c < timeout_ms; c++)
     {
         sb = c1101_getStatus();
-        if (SPIC1101_SB_IDLE(sb))
+        if (CC1101_STATUS_IDLE(sb))
             return true;
         _delay_ms(1);
     }
@@ -597,23 +578,23 @@ bool c1101_writeFrequencyRegisters(uint32_t freq)
     if (! c1101_waitUntilIDLEState(2000)) //wait 2sec max
         return false;
     //programm frequency
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ0, freq & 0xFF);
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ1, (freq >> 8) & 0xFF);
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ2, (freq >> 16) & 0x3F);
+    c1101_spi_write_register(CC1101_REG_RW_FREQ0, freq & 0xFF);
+    c1101_spi_write_register(CC1101_REG_RW_FREQ1, (freq >> 8) & 0xFF);
+    c1101_spi_write_register(CC1101_REG_RW_FREQ2, (freq >> 16) & 0x3F);
 
     //set channel 0
-    c1101_spi_write_register(SPIC1101_ADDR_CHANNR, 0);
+    c1101_spi_write_register(CC1101_REG_RW_CHANNR, 0);
     return true;
 }
 
 uint32_t c1101_readFrequencyRegisters(void)
 {
     uint32_t freq = 0;
-    freq = ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ2)) & 0x3F;
+    freq = ((uint8_t) c1101_spi_read_register(CC1101_REG_RW_FREQ2)) & 0x3F;
     freq = freq << 8;
-    freq |= ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ1));
+    freq |= ((uint8_t) c1101_spi_read_register(CC1101_REG_RW_FREQ1));
     freq = freq << 8;
-    freq |= ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ0));
+    freq |= ((uint8_t) c1101_spi_read_register(CC1101_REG_RW_FREQ0));
     return freq;
 }
 
@@ -621,7 +602,7 @@ uint32_t c1101_readFrequencyRegisters(void)
 // freq:            desired_carrier_freq [Hz] *2^16 / f_XOSC
 bool c1101_setFrequency(uint32_t freq_hz)
 {
-    uint32_t freq = (uint32_t)((float)freq_hz / C1101_FREQ_TO_HZ);
+    uint32_t freq = (uint32_t)((float)freq_hz / CC1101_FREQ_CORR);
     if ( freq <= 0x3FFFFF)
         return c1101_writeFrequencyRegisters(freq);
     else
@@ -632,7 +613,7 @@ bool c1101_setFrequency(uint32_t freq_hz)
 // freq:            desired_carrier_freq [Hz] *2^16 / f_XOSC
 bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz)
 {
-    int32_t freq_change = (int32_t)((float)freq_change_hz / C1101_FREQ_TO_HZ);
+    int32_t freq_change = (int32_t)((float)freq_change_hz / CC1101_FREQ_CORR);
     int32_t freq = (int32_t) c1101_readFrequencyRegisters();
 
     freq += freq_change;
@@ -645,7 +626,7 @@ bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz)
 
 uint32_t c1101_getCurrentCarrierFrequencyHz(void)
 {
-  return (uint32_t)((float)c1101_readFrequencyRegisters() * C1101_FREQ_TO_HZ);
+  return (uint32_t)((float)c1101_readFrequencyRegisters() * CC1101_FREQ_CORR);
 }
 
 // if_freq:         desired intermidiate rx frequency [Hz] *2^10 / f_XOSC
@@ -656,22 +637,22 @@ bool c1101_setIFFrequency(uint32_t freq_hz)
     if (! c1101_waitUntilIDLEState(2000)) //wait 2sec max
         return false;
 
-    c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, if_freq & 0x1F);
+    c1101_spi_write_register(CC1101_REG_RW_FSCTRL1, if_freq & 0x1F);
     return true;
 }
 
-bool c1101_transmitData(char *buffer, uint8_t len)
+bool c1101_transmitData(uint8_t *buffer, uint8_t len)
 {
     //~ uint8_t debug_sb[6];
     uint8_t num_written = 0;
     bool success = true;
-    //~ uint8_t mcsm1 = c1101_spi_read_register(SPIC1101_ADDR_MCSM1);
+    //~ uint8_t mcsm1 = c1101_spi_read_register(CC1101_REG_RW_MCSM1);
     //~ //configure state machine to automatically go to IDLE, once packet was transmitted
     //~ mcsm1 = (mcsm1 & 0b11111100) | 0b00;
-    //~ c1101_spi_write_register(SPIC1101_ADDR_MCSM1, 0x18);
-    //~ c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+    //~ c1101_spi_write_register(CC1101_REG_RW_MCSM1, 0x18);
+    //~ c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
     // flush TX FIFO
-    c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
+    c1101_spi_strobe_command(CC1101_CMD_SFTX);
 
     //~ //fill buffer
     //~ num_written = c1101_spi_write_txfifo(buffer, len);
@@ -691,8 +672,8 @@ bool c1101_transmitData(char *buffer, uint8_t len)
     //~ (debug_sb,255);
 
     //start transmitting
-    //num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX);
-    //~ num_written = hhd70_spi_exchange_byte(SPIC1101_ADDR_STX);
+    //num_written = c1101_spi_strobe_command(CC1101_CMD_STX);
+    //~ num_written = hhd70_spi_exchange_byte(CC1101_CMD_STX);
     //~ ((uint8_t*)"Strobe STX",255);
     //~ debug_sprint_int16hex(debug_sb, num_written);
     //~ (debug_sb,255);
@@ -715,7 +696,7 @@ bool c1101_transmitData(char *buffer, uint8_t len)
             goto c1101_transmitData_cleanup;
         }
         //from state IDLE or RX go to TX
-        num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX);
+        num_written = c1101_spi_strobe_command(CC1101_CMD_STX);
 
         //~ ((uint8_t*)"TX2 num written",255);
         //~ debug_sprint_int16hex(debug_sb, num_written);
@@ -742,10 +723,10 @@ bool c1101_transmitData(char *buffer, uint8_t len)
     return success;
 }
 
-void c1101_transmitData_infPktMode(char *buffer, uint8_t len)
+void c1101_transmitData_infPktMode(uint8_t *buffer, uint8_t len)
 {
     //in infinite Packet Mode, prepend length to buffer:
-    char *new_buffer = malloc(len+1);
+    uint8_t *new_buffer = malloc(len+1);
     new_buffer[0] = len;
     memcpy(new_buffer+1, buffer, len);
     //variable packet length: write length of packet to TX FIFO:
@@ -756,7 +737,7 @@ void c1101_transmitData_infPktMode(char *buffer, uint8_t len)
 void c1101_recieveData(void)
 {
     uint8_t const max_len=255;
-    char recv_data[256];
+    uint8_t recv_data[256];
     uint8_t num_recv = 0;
     uint8_t num_recv_total = 0;
     uint8_t num_leave_in_fifo = 1;
@@ -777,7 +758,7 @@ void c1101_recieveData(void)
 }
 
 //max returned: 64 bytes
-int c1101_readRXFifo(char *buffer)
+int c1101_readRXFifo(uint8_t *buffer)
 {
     //check RXBYTES.NUM_RXBYTES
     // never read more bytes than avaiblabe or we will read garbage
diff --git a/software/hhd70dongle/c1101lib.h b/software/hhd70dongle/c1101lib.h
index e653a4b..f24126b 100644
--- a/software/hhd70dongle/c1101lib.h
+++ b/software/hhd70dongle/c1101lib.h
@@ -30,143 +30,42 @@
  *  along with mur.sat. If not, see <http://www.gnu.org/licenses/>.
  *
  */
-#ifndef  MURSAT_c1101lib_h_INCLUDED__
-#define MURSAT_c1101lib_h_INCLUDED__
-
-#define C1101_FIFO_MAX_LEN 64
+#ifndef MURSAT_c1101lib_h_INCLUDED
+#define MURSAT_c1101lib_h_INCLUDED
 
 #include <stdbool.h>
 
-//read/write config registers:
-#define SPIC1101_ADDR_IOCFG2    0x00
-#define SPIC1101_ADDR_IOCFG1    0x01
-#define SPIC1101_ADDR_IOCFG0    0x02
-#define SPIC1101_ADDR_FIFOTHR   0x03
-#define SPIC1101_ADDR_SYNC1     0x04
-#define SPIC1101_ADDR_SYNC0     0x05
-#define SPIC1101_ADDR_PKTLEN    0x06
-#define SPIC1101_ADDR_PKTCTRL1  0x07
-#define SPIC1101_ADDR_PKTCTRL0  0x08
-#define SPIC1101_ADDR_ADDR      0x09
-#define SPIC1101_ADDR_CHANNR    0x0A
-#define SPIC1101_ADDR_FSCTRL1   0x0B
-#define SPIC1101_ADDR_FSCTRL0   0x0C
-#define SPIC1101_ADDR_FREQ2     0x0D
-#define SPIC1101_ADDR_FREQ1     0x0E
-#define SPIC1101_ADDR_FREQ0     0x0F
-#define SPIC1101_ADDR_MDMCFG4   0x10
-#define SPIC1101_ADDR_MDMCFG3   0x11
-#define SPIC1101_ADDR_MDMCFG2   0x12
-#define SPIC1101_ADDR_MDMCFG1   0x13
-#define SPIC1101_ADDR_MDMCFG0   0x14
-#define SPIC1101_ADDR_DEVIATN   0x15
-#define SPIC1101_ADDR_MCSM2     0x16
-#define SPIC1101_ADDR_MCSM1     0x17
-#define SPIC1101_ADDR_MCSM0     0x18
-#define SPIC1101_ADDR_FOCCFG    0x19
-#define SPIC1101_ADDR_BSCFG     0x1A
-#define SPIC1101_ADDR_AGCCTRL2  0x1B
-#define SPIC1101_ADDR_AGCCTRL1  0x1C
-#define SPIC1101_ADDR_AGCCTRL0  0x1D
-#define SPIC1101_ADDR_WOREVT1   0x1E
-#define SPIC1101_ADDR_WOREVT0   0x1F
-#define SPIC1101_ADDR_WORCTRL   0x20
-#define SPIC1101_ADDR_FREND1    0x21
-#define SPIC1101_ADDR_FREND0    0x22
-#define SPIC1101_ADDR_FSCAL3    0x23
-#define SPIC1101_ADDR_FSCAL2    0x24
-#define SPIC1101_ADDR_FSCAL1    0x25
-#define SPIC1101_ADDR_FSCAL0    0x26
-#define SPIC1101_ADDR_RCCTRL1   0x27
-#define SPIC1101_ADDR_RCCTRL0   0x28
-#define SPIC1101_ADDR_FSTEST    0x29
-#define SPIC1101_ADDR_PTEST     0x2A
-#define SPIC1101_ADDR_AGCTEST   0x2B
-#define SPIC1101_ADDR_TEST2     0x2C
-#define SPIC1101_ADDR_TEST1     0x2D
-#define SPIC1101_ADDR_TEST0     0x2E
-
-//commands:
-#define SPIC1101_ADDR_SRES      0x30
-#define SPIC1101_ADDR_SFSTXON   0x31
-#define SPIC1101_ADDR_SXOFF     0x32
-#define SPIC1101_ADDR_SCAL      0x33
-#define SPIC1101_ADDR_SRX       0x34
-#define SPIC1101_ADDR_STX       0x35
-#define SPIC1101_ADDR_SIDLE     0x36
-#define SPIC1101_ADDR_SWOR      0x38
-#define SPIC1101_ADDR_SPWD      0x39
-#define SPIC1101_ADDR_SFRX      0x3A
-#define SPIC1101_ADDR_SFTX      0x3B
-#define SPIC1101_ADDR_SWORRST   0x3C
-#define SPIC1101_ADDR_SNOP      0x3D
-
-//readonly registers:
-#define SPIC1101_ADDR_PARTNUM        (0x30 | 0xC0)
-#define SPIC1101_ADDR_VERSION        (0x31 | 0xC0)
-#define SPIC1101_ADDR_FREQUEST       (0x32 | 0xC0)
-#define SPIC1101_ADDR_LQI            (0x33 | 0xC0)
-#define SPIC1101_ADDR_RSSI           (0x34 | 0xC0)
-#define SPIC1101_ADDR_MARCSTATE      (0x35 | 0xC0)
-#define SPIC1101_ADDR_WORTIME1       (0x36 | 0xC0)
-#define SPIC1101_ADDR_WORTIME0       (0x37 | 0xC0)
-#define SPIC1101_ADDR_PKTSTATUS      (0x38 | 0xC0)
-#define SPIC1101_ADDR_VCO_VC_DAC     (0x39 | 0xC0)
-#define SPIC1101_ADDR_TXBYTES        (0x3A | 0xC0)
-#define SPIC1101_ADDR_RXBYTES        (0x3B | 0xC0)
-#define SPIC1101_ADDR_RCCTRL1_STATUS (0x3C | 0xC0)
-#define SPIC1101_ADDR_RCCTRL0_STATUS (0x3D | 0xC0)
-
-#define SPIC1101_ADDR_FIFO_READ (0x3F | 0x80)
-#define SPIC1101_ADDR_FIFO_READ_BURST (0x3F | 0x80 | 0xC0)
-#define SPIC1101_ADDR_FIFO_WRITE 0x3F
-#define SPIC1101_ADDR_FIFO_WRITE_BURST (0x3F | 0x40)
-
-#define SPIC1101_ADDR_PATABLE_READ (0x3E | 0x80)
-#define SPIC1101_ADDR_PATABLE_READ_BURST (0x3E | 0x80 | 0xC0)
-#define SPIC1101_ADDR_PATABLE_WRITE 0x3E
-#define SPIC1101_ADDR_PATABLE_WRITE_BURST (0x3E | 0x40)
-
-
-#define SPIC1101_SB_CHIP_NOT_RDY(x) (x & 0b10000000)
-#define SPIC1101_SB_IDLE(x) (x & 0b01110000) == 0
-#define SPIC1101_SB_RXMODE(x) (x & 0b01110000) == 0b0010000
-#define SPIC1101_SB_TXMODE(x) (x & 0b01110000) == 0b0100000
-#define SPIC1101_SB_FSTXON(x) (x & 0b01110000) == 0b0110000
-#define SPIC1101_SB_CALIBRATE(x) (x & 0b01110000) == 0b1000000
-#define SPIC1101_SB_SETTLING(x) (x & 0b01110000) == 0b1010000
-#define SPIC1101_SB_RXFIFO_OVERFLOW(x) (x & 0b01110000) == 0b1100000
-#define SPIC1101_SB_TXFIFO_OVERFLOW(x) (x & 0b01110000) == 0b1110000
-#define SPIC1101_SB_FIFO_BYTES_AVAILABLE(x) (x & 0b00001111)
-
-#define C1101_FREQ_TO_HZ 396.728515 // = Fosc/65536 = 26000000/65536
+// TODO: should be internal only...
+int16_t c1101_spi_read_register(uint8_t address);
+int16_t c1101_spi_write_register(uint8_t address, uint8_t byte);
+int16_t c1101_spi_strobe_command(uint8_t cmd);
 
-int16_t c1101_spi_read_register(char address);
-int16_t c1101_spi_write_register(char address, char byte);
-int16_t c1101_spi_strobe_command(char address);
-
-uint16_t c1101_setFSKDeviationFromCarrier(int8_t m, int8_t e);
 void c1101_init(void);
 void c1101_init_ook_beacon(void);
+
 uint8_t c1101_ook_power_get(void);
 uint8_t c1101_ook_power_get_raw(void);
 void c1101_ook_power_set(uint8_t power);
 void c1101_ook_power_inc(void);
 void c1101_ook_power_dec(void);
-void c1101_handleStatusByte(char sb);
-char c1101_getStatus(void);
+
+void c1101_handleStatusByte(uint8_t sb);
+uint8_t c1101_getStatus(void);
+
 uint16_t c1101_measureTemp(void);
-void c1101_spi_dump_registers_to_usb(void);
+void c1101_spi_dump_registers(void);
 void c1101_permanently_save_current_rx_tx_freqoffset_auto_compensation(void);
 bool c1101_setFrequency(uint32_t freq_hz);
 bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz);
 uint32_t c1101_getCurrentCarrierFrequencyHz(void);
 bool c1101_setIFFrequency(uint32_t freq_hz);
-bool c1101_transmitData(char *buffer, uint8_t len);
-void c1101_transmitData_infPktMode(char *buffer, uint8_t len);
+uint16_t c1101_setFSKDeviationFromCarrier(int8_t m, int8_t e);
+
+bool c1101_transmitData(uint8_t *buffer, uint8_t len);
+void c1101_transmitData_infPktMode(uint8_t *buffer, uint8_t len);
 void c1101_recieveData(void);
 
 //max returned: 64 bytes
-int c1101_readRXFifo(char *buffer);
+int c1101_readRXFifo(uint8_t *buffer);
 
 #endif
diff --git a/software/hhd70dongle/hhd70dongle.c b/software/hhd70dongle/hhd70dongle.c
index 81fabf4..f28886d 100644
--- a/software/hhd70dongle/hhd70dongle.c
+++ b/software/hhd70dongle/hhd70dongle.c
@@ -43,6 +43,7 @@
 
 #include "hhd70.h"
 #include "c1101lib.h"
+#include "cc1101_defines.h"
 
 //todo: move to separte File:
 
@@ -95,7 +96,7 @@ void print_part_status(void)
 
 void beacon_enable(void)
 {
-    c1101_spi_strobe_command(SPIC1101_ADDR_STX);
+    c1101_spi_strobe_command(CC1101_CMD_STX);
     hhd70_palna_txmode();
 }
 
@@ -114,7 +115,7 @@ void beacon_off(void)
 void beacon_disable(void)
 {
     hhd70_palna_rxmode();
-    c1101_spi_strobe_command(SPIC1101_ADDR_SIDLE);
+    c1101_spi_strobe_command(CC1101_CMD_SIDLE);
 }
 
 int main(void)
@@ -133,7 +134,7 @@ int main(void)
     printf("hhd70dongle ready\r\n");
 
     _delay_ms(500);
-    c1101_spi_strobe_command(SPIC1101_ADDR_SRES); // reset c1101
+    c1101_spi_strobe_command(CC1101_CMD_SRES); // reset c1101
     //c1101 init now happens after pressing B, S or E
 
     hhd70_palna_rxmode();
@@ -170,7 +171,7 @@ int main(void)
               enable_tx_part=false;
               enable_rx_part=false;
               enable_beacon_part=false;
-              c1101_spi_strobe_command(SPIC1101_ADDR_SRES); // reset c1101
+              c1101_spi_strobe_command(CC1101_CMD_SRES); // reset c1101
               hhd70_palna_rxmode();
               print_part_status();
               led_off();
@@ -213,7 +214,7 @@ int main(void)
             }
             else if ((char) recv_byte == 'R')
             {
-                c1101_spi_dump_registers_to_usb();
+                c1101_spi_dump_registers();
                 print_part_status();
             }
             else if ((char) recv_byte == 'D' || (char) recv_byte == 'd')
@@ -334,13 +335,13 @@ int main(void)
             }
         }
 
-        
+
         usbio_task();
 
         if (enable_rx_part)
         {
 
-            c1101_spi_strobe_command(SPIC1101_ADDR_SRX); // enter RX - Mode
+            c1101_spi_strobe_command(CC1101_CMD_SRX); // enter RX - Mode
             _delay_ms(1000);
 
             if (hhd70_rx_data_available())
@@ -348,7 +349,7 @@ int main(void)
                 led_on();
                 printf("RX: GDO2 pin HIGH\r\n");
                 printf("c1101 rx bytes:");
-                debug_sprint_int16hex(write_buffer, c1101_spi_read_register(SPIC1101_ADDR_RXBYTES));
+                debug_sprint_int16hex(write_buffer, c1101_spi_read_register(CC1101_REG_RO_RXBYTES));
                 printf("%s", write_buffer);
                 printf("\r\n");
                 c1101_recieveData();
@@ -356,15 +357,15 @@ int main(void)
             }
 
             printf("c1101 rssi: ");
-            debug_sprint_int16hex(write_buffer, c1101_spi_read_register(SPIC1101_ADDR_RSSI));
+            debug_sprint_int16hex(write_buffer, c1101_spi_read_register(CC1101_REG_RO_RSSI));
             printf("%s", write_buffer);
             printf("\r\n");
             printf("c1101 tx bytes: ");
-            debug_sprint_int16hex(write_buffer, c1101_spi_read_register(SPIC1101_ADDR_TXBYTES));
+            debug_sprint_int16hex(write_buffer, c1101_spi_read_register(CC1101_REG_RO_TXBYTES));
             printf("%s", write_buffer);
             printf("\r\n");
             printf("c1101 rx bytes: ");
-            int16_t num_rx_bytes = c1101_spi_read_register(SPIC1101_ADDR_RXBYTES);
+            int16_t num_rx_bytes = c1101_spi_read_register(CC1101_REG_RO_RXBYTES);
             debug_sprint_int16hex(write_buffer, num_rx_bytes);
             printf("%s", write_buffer);
             printf("\r\n");
@@ -408,7 +409,7 @@ int main(void)
             /* _delay_ms(250); */
             /* led_on(); */
             /* printf("TX Data: String\r\n"); */
-            c1101_transmitData_infPktMode("OE6EOF test mur.sat GFSK r:9k6 fdev:11kHz 1234567890123456789012345678901234567890 End of Test",93);
+            /* c1101_transmitData_infPktMode("OE6EOF test mur.sat GFSK r:9k6 fdev:11kHz 1234567890123456789012345678901234567890 End of Test",93); */
             /* led_off(); */
             /* _delay_ms(100); */
             /* led_on(); */
@@ -424,12 +425,12 @@ int main(void)
             led_on();
             //c1101_transmitData_infPktMode(mursat_beacon,sizeof(mursat_beacon));
             hhd70_palna_txmode();
-            c1101_spi_strobe_command(SPIC1101_ADDR_STX);
+            c1101_spi_strobe_command(CC1101_CMD_STX);
             hhd70_set_OOK_GDO0_high();
             _delay_ms(1000);
             led_off();
             hhd70_set_OOK_GDO0_low();
-            c1101_spi_strobe_command(SPIC1101_ADDR_SIDLE);
+            c1101_spi_strobe_command(CC1101_CMD_SIDLE);
             hhd70_palna_rxmode();
             _delay_ms(200);
             }*/