diff options
Diffstat (limited to 'software/hhd70dongle/c1101lib.c')
| -rw-r--r-- | software/hhd70dongle/c1101lib.c | 517 |
1 files changed, 249 insertions, 268 deletions
diff --git a/software/hhd70dongle/c1101lib.c b/software/hhd70dongle/c1101lib.c index c24c398..209ccee 100644 --- a/software/hhd70dongle/c1101lib.c +++ b/software/hhd70dongle/c1101lib.c @@ -31,198 +31,178 @@ * */ #include <stdlib.h> +#include <stdio.h> +#include <string.h> #include <avr/io.h> #include <util/delay.h> #include "c1101lib.h" +#include "cc1101_defines.h" #include "hhd70.h" #include "util.h" -/**** Helper Functions ****/ +// internal functions -#define SPIC1101_MAX_WAIT 21 +#define CC1101_MAX_WAIT_RDY 21 - - -/* ###### ###### - LUFA Library - Copyright (C) Dean Camera, 2012. - - dean [at] fourwalledcubicle [dot] com - www.lufa-lib.org -*/ -//#include <LUFA/Drivers/Misc/RingBuffer.h> -#include <LUFA/Drivers/USB/USB.h> - - /* Global I/O Buffers: */ -//static RingBuffer_t SPItoUSB_Buffer; -//static uint8_t SPItoUSB_Buffer_Data[8]; - - -int16_t c1101_spi_write_byte_ok_get_status(char data) +static int16_t c1101_spi_write_byte_ok_get_status(uint8_t data) { - //~ uint8_t debug_sb[6]; - char sb; - unsigned int attempts = 0; - do - { - sb = hhd70_spi_exchange_byte(data); + uint8_t sb; + unsigned int attempts = 0; + do + { + sb = hhd70_spi_exchange_byte(data); //Note: content of returned StatusByte is actually context depenedant on sent command // i.e. we won't get Fifo Byte count or overflow status on normal command and so on // e.g. we only get TX Fifo Free Byte count while writing to TX Fifo // thus it makes sense to only check for CHIP_RDY here - //~ ((uint8_t*)"spi byte exchanged ",255); - //~ debug_sprint_int16hex(debug_sb, sb); - //~ (debug_sb,255); - if (attempts++ > SPIC1101_MAX_WAIT) - return -1; - } while ( SPIC1101_SB_CHIP_NOT_RDY(sb) ); - return sb; + if (attempts++ > CC1101_MAX_WAIT_RDY) + return -1; + } while (CC1101_STATUS_CHIP_NOT_RDY(sb)); + return sb; } -int16_t c1101_spi_strobe_command(char address) +int16_t c1101_spi_strobe_command(uint8_t cmd) { - char rbyte; - if (address < 0x30) - return -1; - hhd70_spi_cs_enable(); - hhd70_c1101_wait_chip_rdy(); - //POST DEBUG: don't return anything - rbyte = c1101_spi_write_byte_ok_get_status(address); - if (rbyte < 0) - return -1; - hhd70_spi_cs_disable(); - return rbyte; + if(cmd < CC1101_CMD_MIN || cmd > CC1101_CMD_MAX) + return -1; + + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + uint8_t rbyte = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_COMMAND | cmd); + if(rbyte < 0) + return -1; + hhd70_spi_cs_disable(); + return rbyte; } -// note addresses range from 0x00 to 0x2F for normal registers and 0xF0 to 0xFD for special status registers -int16_t c1101_spi_read_register(char address) +int16_t c1101_spi_read_register(uint8_t addr) { - char rbyte; - if (address < 0x30) - address |= 0x80; - else - address |= 0xC0; - hhd70_spi_cs_enable(); - hhd70_c1101_wait_chip_rdy(); - if (c1101_spi_write_byte_ok_get_status(address) < 0) - return -1; - rbyte = hhd70_spi_read_byte(); - hhd70_spi_cs_disable(); - return rbyte; + if(addr > CC1101_ADDR_MAX) + return -1; + + if(addr > CC1101_REG_RW_MAX) + addr |= CC1101_HEADER_READONLY; + else + addr |= CC1101_HEADER_READ; + + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + if(c1101_spi_write_byte_ok_get_status(addr) < 0) + return -1; + uint8_t rbyte = hhd70_spi_read_byte(); + hhd70_spi_cs_disable(); + return rbyte; } -// note addresses range from 0x00 to 0x2F for normal registers -int16_t c1101_spi_write_register(char address, char byte) +int16_t c1101_spi_write_register(uint8_t addr, uint8_t byte) { - hhd70_spi_cs_enable(); - hhd70_c1101_wait_chip_rdy(); - if (c1101_spi_write_byte_ok_get_status(address & 0x3F) < 0) - return -1; - _delay_ms(2); - if (c1101_spi_write_byte_ok_get_status(byte) < 0) - return -1; - hhd70_spi_cs_disable(); - return 1; + if(addr > CC1101_REG_RW_MAX) + return -1; + + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + if(c1101_spi_write_byte_ok_get_status(CC1101_HEADER_WRITE | addr) < 0) + return -1; + _delay_ms(2); // TODO: why wait here??? + if(c1101_spi_write_byte_ok_get_status(byte) < 0) + return -1; + hhd70_spi_cs_disable(); + return 1; } -void c1101_spi_dump_registers_to_usb(void) +void c1101_spi_dump_registers(void) { - int c = 0; - char debug_sb[6]; - hhd70_spi_cs_enable(); - hhd70_c1101_wait_chip_rdy(); - if (c1101_spi_write_byte_ok_get_status(0xC0) < 0) - return; - printf("dump all 46 registers:\r\n"); - for (c=0; c<47; c++) - { - debug_sprint_int16hex(debug_sb, hhd70_spi_read_byte()); - printf("%s", debug_sb); - printf("\r\n"); - } - hhd70_spi_cs_disable(); + int c = 0; + char debug_sb[6]; + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + if (c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | 0x00) < 0) + return; + printf("dump all 46 registers:\r\n"); + for (c = 0; c < CC1101_REG_RW_MAX; c++) { + debug_sprint_int16hex(debug_sb, hhd70_spi_read_byte()); + printf("%s", debug_sb); + printf("\r\n"); + } + hhd70_spi_cs_disable(); } -int c1101_spi_read_rxfifo(int leave_num_bytes, char *buffer, int maxlen) +int c1101_spi_read_rxfifo(int leave_num_bytes, uint8_t *buffer, int maxlen) { - int num_read = 0; - uint8_t num_available = 0; - hhd70_spi_cs_enable(); - hhd70_c1101_wait_chip_rdy(); - if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_RXBYTES) < 0) - return -1; - num_available = hhd70_spi_read_byte(); - if (num_available == 0) - return 0; - if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST) < 0) - return -1; - while (maxlen-- > 0 && num_available - num_read > leave_num_bytes) - { - buffer[num_read++] = hhd70_spi_read_byte(); - } - hhd70_spi_cs_disable(); - return num_read; + int num_read = 0; + uint8_t num_available = 0; + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + if (c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READONLY | CC1101_REG_RO_RXBYTES) < 0) + return -1; + + num_available = hhd70_spi_read_byte(); + if (num_available == 0) + return 0; + if (c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | CC1101_REG_FIFO) < 0) + return -1; + while (maxlen-- > 0 && num_available - num_read > leave_num_bytes) + buffer[num_read++] = hhd70_spi_read_byte(); + + hhd70_spi_cs_disable(); + return num_read; } //note: currently this function reads at most 15 bytes -int c1101_spi_read_rxfifo_max15(int leave_num_bytes, char *buffer, int maxlen) -{ - int16_t sb; - int num_read = 0; - hhd70_spi_cs_enable(); - hhd70_c1101_wait_chip_rdy(); - sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST); - if (sb < 0) - return -1; - //note if SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) == 15 then 15 or more bytes are available - while (maxlen-- > 0 && SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) - num_read > leave_num_bytes) - { +int c1101_spi_read_rxfifo_max15(int leave_num_bytes, uint8_t *buffer, int maxlen) +{ + int16_t sb; + int num_read = 0; + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | CC1101_REG_FIFO); + if (sb < 0) + return -1; + //note if CC1101_STATUS_FIFO_BYTES_AVAILABLE(sb) == 15 then 15 or more bytes are available + while (maxlen-- > 0 && CC1101_STATUS_FIFO_BYTES_AVAILABLE(sb) - num_read > leave_num_bytes) { //hope this works !! - buffer[num_read++] = hhd70_spi_read_byte(); - } - hhd70_spi_cs_disable(); - return num_read; + buffer[num_read++] = hhd70_spi_read_byte(); + } + hhd70_spi_cs_disable(); + return num_read; } //note: always check if num_written returned == len given -int c1101_spi_write_txfifo(char *buffer, int len) -{ - char sb; - int num_written = 0; - hhd70_spi_cs_enable(); - hhd70_c1101_wait_chip_rdy(); - sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_WRITE_BURST); - if (sb < 0) - return -1; - while (len-- > 0 && SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) > 2) - { - sb = c1101_spi_write_byte_ok_get_status(buffer[num_written++]); - } - hhd70_spi_cs_disable(); - return num_written; -} - -//patable muste be char array of length 8 +int c1101_spi_write_txfifo(uint8_t *buffer, int len) +{ + uint8_t sb; + int num_written = 0; + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | CC1101_REG_FIFO); + if (sb < 0) + return -1; + while (len-- > 0 && CC1101_STATUS_FIFO_BYTES_AVAILABLE(sb) > 2) { + sb = c1101_spi_write_byte_ok_get_status(buffer[num_written++]); + } + hhd70_spi_cs_disable(); + return num_written; +} + +//patable muste be uint8_t array of length 8 int c1101_spi_write_patable(uint8_t const patable[]) { - int16_t sb; - int8_t len = 8; - hhd70_spi_cs_enable(); - hhd70_c1101_wait_chip_rdy(); - sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_PATABLE_WRITE_BURST); - if (sb < 0) - return -1; - while (len-- > 0) - { - sb = c1101_spi_write_byte_ok_get_status(*patable); - patable++; - } - hhd70_spi_cs_disable(); - return sb; + int16_t sb; + int8_t len = 8; + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_WRITE | CC1101_HEADER_BURST | CC1101_REG_PATABLE); + if (sb < 0) + return -1; + while (len-- > 0) { + sb = c1101_spi_write_byte_ok_get_status(*patable); + patable++; + } + hhd70_spi_cs_disable(); + return sb; } - static uint8_t const pa_table_values_[] = { 0x00, 0x30, 0x20, 0x10, 0x01, 0x02, 0x11, 0x03, 0x12, 0x04, 0x05, 0x13, 0x06, 0x07, 0x21, 0x14, 0x08, 0x09, 0x0A, 0x15, 0x0B, 0x31, 0x16, 0x0C, 0x0D, 0x0E, 0x17, 0x0F, 0x22, 0x18, 0x19, 0x1A, @@ -238,69 +218,70 @@ static uint8_t const pa_table_values_[] = { 0x00, 0x30, 0x20, 0x10, 0x01, 0x02, #define PA_TABLE_VALUES_MAX ((sizeof(pa_table_values_)/sizeof(uint8_t))-1) static uint8_t ook_power_ = 83; // ==> 3F + /**** External Functions ****/ uint16_t c1101_setFSKDeviationFromCarrier(int8_t m, int8_t e) { - c1101_spi_write_register(SPIC1101_ADDR_DEVIATN, (m & 0x7) | ((e & 0x7) << 4)); + c1101_spi_write_register(CC1101_REG_RW_DEVIATN, (m & 0x7) | ((e & 0x7) << 4)); return (1983u * (8u+((uint32_t)m)) * (1u << ((uint32_t)e))) / 100; //return +- deviation in 10Hz Steps } void c1101_init(void) { //reset C1101 - c1101_spi_strobe_command(SPIC1101_ADDR_SRES); + c1101_spi_strobe_command(CC1101_CMD_SRES); _delay_ms(100); //flush FIFOs - c1101_spi_strobe_command(SPIC1101_ADDR_SFRX); - c1101_spi_strobe_command(SPIC1101_ADDR_SFTX); - //dump pre-init default values to usb - c1101_spi_dump_registers_to_usb(); + c1101_spi_strobe_command(CC1101_CMD_SFRX); + c1101_spi_strobe_command(CC1101_CMD_SFTX); + //dump pre-init default values to stdout + c1101_spi_dump_registers(); //enable analog temperature sensor on GDO0 - c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x80); + c1101_spi_write_register(CC1101_REG_RW_IOCFG0, 0x80); //enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO) - c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47 + c1101_spi_write_register(CC1101_REG_RW_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47 // FIFOTHR RX FIFO and TX FIFO Thresholds // pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx) - //c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 2); //assert at 12 bytes in RX Fifo and 53 in TX Fifo - c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 0); //assert at 4 bytes in RX Fifo and 61 in TX Fifo + //c1101_spi_write_register(CC1101_REG_RW_FIFOTHR, 2); //assert at 12 bytes in RX Fifo and 53 in TX Fifo + c1101_spi_write_register(CC1101_REG_RW_FIFOTHR, 0); //assert at 4 bytes in RX Fifo and 61 in TX Fifo // PKTCTRL0 Packet Automation Control - //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode - c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) - //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000101); //crc enabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) - c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet + //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode + c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) + //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000101); //crc enabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) + c1101_spi_write_register(CC1101_REG_RW_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet // FSCTRL1 Frequency Synthesizer Control - c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, 0x06); + c1101_spi_write_register(CC1101_REG_RW_FSCTRL1, 0x06); // FREQn Frequency Control Words - c1101_spi_write_register(SPIC1101_ADDR_FREQ2, 0x10); //should be 435.125 mhz - c1101_spi_write_register(SPIC1101_ADDR_FREQ1, 0xBF); - c1101_spi_write_register(SPIC1101_ADDR_FREQ0, 0xEF); - c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, 0); //frequency offset + c1101_spi_write_register(CC1101_REG_RW_FREQ2, 0x10); //should be 435.125 mhz + c1101_spi_write_register(CC1101_REG_RW_FREQ1, 0xBF); + c1101_spi_write_register(CC1101_REG_RW_FREQ0, 0xEF); + c1101_spi_write_register(CC1101_REG_RW_FSCTRL0, 0); //frequency offset // MDMCFGn Modem Configuration - c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4, 0xF8); - c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3, 0x83); - c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2, 0x12); //gfsk, 15/16 sync word - c1101_spi_write_register(SPIC1101_ADDR_MDMCFG1, 0x00); + c1101_spi_write_register(CC1101_REG_RW_MDMCFG4, 0xF8); + c1101_spi_write_register(CC1101_REG_RW_MDMCFG3, 0x83); + c1101_spi_write_register(CC1101_REG_RW_MDMCFG2, 0x12); //gfsk, 15/16 sync word + c1101_spi_write_register(CC1101_REG_RW_MDMCFG1, 0x00); //Sync Word - c1101_spi_write_register(SPIC1101_ADDR_SYNC1, 0x21); - c1101_spi_write_register(SPIC1101_ADDR_SYNC0, 0x42); + c1101_spi_write_register(CC1101_REG_RW_SYNC1, 0x21); + c1101_spi_write_register(CC1101_REG_RW_SYNC0, 0x42); // DEVIATN Modem Deviation Setting - c1101_spi_write_register(SPIC1101_ADDR_DEVIATN, 0x11); //0x11 equals deviation of 3.5kHz; 0x27 equals deviation of 11.9kHz + c1101_spi_write_register(CC1101_REG_RW_DEVIATN, 0x11); //0x11 equals deviation of 3.5kHz; 0x27 equals deviation of 11.9kHz // MCSM0 Main Radio Control State Machine Configuration - c1101_spi_write_register(SPIC1101_ADDR_MCSM0, 0x18); - c1101_spi_write_register(SPIC1101_ADDR_MCSM1, 0b00111100); // State RX after recieving packet-> stay in RX; State TX after sending packet -> IDLE + c1101_spi_write_register(CC1101_REG_RW_MCSM0, 0x18); + c1101_spi_write_register(CC1101_REG_RW_MCSM1, 0b00111100); // State RX after recieving packet-> stay in RX; State TX after sending packet -> IDLE // FOCCFG Frequency Offset Compensation Configuration - c1101_spi_write_register(SPIC1101_ADDR_FOCCFG, 0x16); + c1101_spi_write_register(CC1101_REG_RW_FOCCFG, 0x16); // WORCTRL Wake On Radio Control - c1101_spi_write_register(SPIC1101_ADDR_WORCTRL, 0xFB); + c1101_spi_write_register(CC1101_REG_RW_WORCTRL, 0xFB); // FSCALn Frequency Synthesizer Calibration - c1101_spi_write_register(SPIC1101_ADDR_FSCAL3, 0xE9); - c1101_spi_write_register(SPIC1101_ADDR_FSCAL2, 0x2A); - c1101_spi_write_register(SPIC1101_ADDR_FSCAL1, 0x00); - c1101_spi_write_register(SPIC1101_ADDR_FSCAL0, 0x1F); + c1101_spi_write_register(CC1101_REG_RW_FSCAL3, 0xE9); + c1101_spi_write_register(CC1101_REG_RW_FSCAL2, 0x2A); + c1101_spi_write_register(CC1101_REG_RW_FSCAL1, 0x00); + c1101_spi_write_register(CC1101_REG_RW_FSCAL0, 0x1F); //FREN0 TX Power: - c1101_spi_write_register(SPIC1101_ADDR_FREND0, 0x10); //should be set using RF-Studio !!, for now, only use PA-Table Entry[0] no power ramping !! (FIXME: but should maybe be used) - c1101_spi_write_register(SPIC1101_ADDR_PATABLE_WRITE, 0xC0); //write PATABLE[0] only, rest needs to be written in Burst-Mode ! set to max power 10dBm + c1101_spi_write_register(CC1101_REG_RW_FREND0, 0x10); //should be set using RF-Studio !!, for now, only use PA-Table Entry[0] no power ramping !! (FIXME: but should maybe be used) + c1101_spi_write_register(CC1101_REG_PATABLE, 0xC0); //write PATABLE[0] only, rest needs to be written in Burst-Mode ! set to max power 10dBm // note: for now: assume f_xosc to be 26 Mhz // for ~433.125 Mhz -> freq = 1091741, freq_offset = 0 @@ -341,15 +322,15 @@ void c1101_init_w_rfstudiosettings1(void) // Rf settings for CC1101 // //reset C1101 - c1101_spi_strobe_command(SPIC1101_ADDR_SRES); + c1101_spi_strobe_command(CC1101_CMD_SRES); _delay_ms(100); //flush FIFOs - c1101_spi_strobe_command(SPIC1101_ADDR_SFRX); - c1101_spi_strobe_command(SPIC1101_ADDR_SFTX); + c1101_spi_strobe_command(CC1101_CMD_SFRX); + c1101_spi_strobe_command(CC1101_CMD_SFTX); //enable analog temperature sensor on GDO0 - c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x80); + c1101_spi_write_register(CC1101_REG_RW_IOCFG0, 0x80); //enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO) - c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47 + c1101_spi_write_register(CC1101_REG_RW_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47 //Values from SmartRFStudio: c1101_spi_write_patable(pa_table); @@ -382,41 +363,41 @@ void c1101_init_ook_beacon(void) // PA table by TI //reset C1101 - c1101_spi_strobe_command(SPIC1101_ADDR_SRES); + c1101_spi_strobe_command(CC1101_CMD_SRES); _delay_ms(100); //flush FIFOs - c1101_spi_strobe_command(SPIC1101_ADDR_SFRX); - c1101_spi_strobe_command(SPIC1101_ADDR_SFTX); + c1101_spi_strobe_command(CC1101_CMD_SFRX); + c1101_spi_strobe_command(CC1101_CMD_SFTX); // // Rf settings for CC1101 // - c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x00); + c1101_spi_write_register(CC1101_REG_RW_IOCFG0, 0x00); //enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO) - c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47 + c1101_spi_write_register(CC1101_REG_RW_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47 // pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx) - //c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds - c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 0); //assert at 4 bytes in RX Fifo and 61 in TX Fifo - //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0,0x12);//Packet Automation Control - //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) - c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000110001); //crc disabled; asynchronous serial input on GDO0 - c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1,0x06); //Frequency Synthesizer Control - c1101_spi_write_register(SPIC1101_ADDR_FREQ2,0x10); //Frequency Control Word, High Byte - c1101_spi_write_register(SPIC1101_ADDR_FREQ1,0xD3); //Frequency Control Word, Middle Byte - c1101_spi_write_register(SPIC1101_ADDR_FREQ0,0xF0); //Frequency Control Word, Low Byte - c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4,0xF5); //Modem Configuration - c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3,0x43); //Modem Configuration - c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2,0x30); //Modem Configuration - c1101_spi_write_register(SPIC1101_ADDR_MDMCFG1,0x00); //Modem Configuration - c1101_spi_write_register(SPIC1101_ADDR_DEVIATN,0x07); //Modem Deviation Setting - c1101_spi_write_register(SPIC1101_ADDR_MCSM0,0x18); //Main Radio Control State Machine Configuration - c1101_spi_write_register(SPIC1101_ADDR_FOCCFG,0x16); //Frequency Offset Compensation Configuration - c1101_spi_write_register(SPIC1101_ADDR_WORCTRL,0xFB); //Wake On Radio Control - c1101_spi_write_register(SPIC1101_ADDR_FREND0,0x11); //Front End TX Configuration // PA_POWER[2:0] = 1 - c1101_spi_write_register(SPIC1101_ADDR_FSCAL3,0xE9); //Frequency Synthesizer Calibration - c1101_spi_write_register(SPIC1101_ADDR_FSCAL2,0x2A); //Frequency Synthesizer Calibration - c1101_spi_write_register(SPIC1101_ADDR_FSCAL1,0x00); //Frequency Synthesizer Calibration - c1101_spi_write_register(SPIC1101_ADDR_FSCAL0,0x1F); //Frequency Synthesizer Calibration + //c1101_spi_write_register(CC1101_REG_RW_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds + c1101_spi_write_register(CC1101_REG_RW_FIFOTHR, 0); //assert at 4 bytes in RX Fifo and 61 in TX Fifo + //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0,0x12);//Packet Automation Control + //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) + c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000110001); //crc disabled; asynchronous serial input on GDO0 + c1101_spi_write_register(CC1101_REG_RW_FSCTRL1,0x06); //Frequency Synthesizer Control + c1101_spi_write_register(CC1101_REG_RW_FREQ2,0x10); //Frequency Control Word, High Byte + c1101_spi_write_register(CC1101_REG_RW_FREQ1,0xD3); //Frequency Control Word, Middle Byte + c1101_spi_write_register(CC1101_REG_RW_FREQ0,0xF0); //Frequency Control Word, Low Byte + c1101_spi_write_register(CC1101_REG_RW_MDMCFG4,0xF5); //Modem Configuration + c1101_spi_write_register(CC1101_REG_RW_MDMCFG3,0x43); //Modem Configuration + c1101_spi_write_register(CC1101_REG_RW_MDMCFG2,0x30); //Modem Configuration + c1101_spi_write_register(CC1101_REG_RW_MDMCFG1,0x00); //Modem Configuration + c1101_spi_write_register(CC1101_REG_RW_DEVIATN,0x07); //Modem Deviation Setting + c1101_spi_write_register(CC1101_REG_RW_MCSM0,0x18); //Main Radio Control State Machine Configuration + c1101_spi_write_register(CC1101_REG_RW_FOCCFG,0x16); //Frequency Offset Compensation Configuration + c1101_spi_write_register(CC1101_REG_RW_WORCTRL,0xFB); //Wake On Radio Control + c1101_spi_write_register(CC1101_REG_RW_FREND0,0x11); //Front End TX Configuration // PA_POWER[2:0] = 1 + c1101_spi_write_register(CC1101_REG_RW_FSCAL3,0xE9); //Frequency Synthesizer Calibration + c1101_spi_write_register(CC1101_REG_RW_FSCAL2,0x2A); //Frequency Synthesizer Calibration + c1101_spi_write_register(CC1101_REG_RW_FSCAL1,0x00); //Frequency Synthesizer Calibration + c1101_spi_write_register(CC1101_REG_RW_FSCAL0,0x1F); //Frequency Synthesizer Calibration c1101_ook_power_set(ook_power_); hhd70_config_GDO0_OOK_output(true); @@ -459,81 +440,81 @@ void c1101_ook_power_dec() void c1101_permanently_save_current_rx_tx_freqoffset_auto_compensation() { int16_t freq_offset; - freq_offset = c1101_spi_read_register(SPIC1101_ADDR_FREQUEST); + freq_offset = c1101_spi_read_register(CC1101_REG_RO_FREQUEST); if (freq_offset >= 0) { - c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, (uint8_t) freq_offset); + c1101_spi_write_register(CC1101_REG_RW_FSCTRL0, (uint8_t) freq_offset); } } // WARNING: All content of the PATABLE except for the first byte (index 0) is lost when entering the SLEEP state. -char c1101_putToSleep(void) +uint8_t c1101_putToSleep(void) { - return c1101_spi_strobe_command(SPIC1101_ADDR_SPWD); + return c1101_spi_strobe_command(CC1101_CMD_SPWD); } uint16_t c1101_measureTemp(void) { uint16_t temp; - char ptest_value=0x7F; - ptest_value = c1101_spi_read_register(SPIC1101_ADDR_PTEST); - c1101_spi_write_register(SPIC1101_ADDR_PTEST, 0xBF); + uint8_t ptest_value=0x7F; + ptest_value = c1101_spi_read_register(CC1101_REG_RW_PTEST); + c1101_spi_write_register(CC1101_REG_RW_PTEST, 0xBF); _delay_ms(5); temp = adc_read(ADCMUX_INTERNALTEMP); - c1101_spi_write_register(SPIC1101_ADDR_PTEST, ptest_value); + c1101_spi_write_register(CC1101_REG_RW_PTEST, ptest_value); return temp; } -void c1101_handleMARCStatusByte(char sb) +void c1101_handleMARCStatusByte(uint8_t sb) { //on RXFifo Overflow, Flush RX Fifo if (sb == 0x11) { - c1101_spi_strobe_command(SPIC1101_ADDR_SFRX); + c1101_spi_strobe_command(CC1101_CMD_SFRX); printf("RX fifo flushed\r\n"); } //on TXFifo Overflow, Flush TX Fifo else if (sb == 0x16) { - c1101_spi_strobe_command(SPIC1101_ADDR_SFTX); + c1101_spi_strobe_command(CC1101_CMD_SFTX); printf("TX fifo flushed\r\n"); } } -void c1101_handleStatusByte(char sb) +void c1101_handleStatusByte(uint8_t sb) { //on RXFifo Overflow, Flush RX Fifo - if (SPIC1101_SB_RXFIFO_OVERFLOW(sb)) + if (CC1101_STATUS_RXFIFO_OVERFLOW(sb)) { - c1101_spi_strobe_command(SPIC1101_ADDR_SFRX); + c1101_spi_strobe_command(CC1101_CMD_SFRX); printf("RX fifo flushed\r\n"); } //on TXFifo Overflow, Flush TX Fifo - if (SPIC1101_SB_TXFIFO_OVERFLOW(sb)) + if (CC1101_STATUS_TXFIFO_OVERFLOW(sb)) { - c1101_spi_strobe_command(SPIC1101_ADDR_SFTX); + c1101_spi_strobe_command(CC1101_CMD_SFTX); printf("TX fifo flushed\r\n"); } } -char c1101_getStatus(void) +uint8_t c1101_getStatus(void) { - char sb=0; + uint8_t sb=0; hhd70_spi_cs_enable(); hhd70_c1101_wait_chip_rdy(); - sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_SNOP); + sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_COMMAND | CC1101_CMD_SNOP); hhd70_spi_cs_disable(); c1101_handleStatusByte(sb); return sb; } -char c1101_getMARCState(void) +uint8_t c1101_getMARCState(void) { - char sb=0; - sb = c1101_spi_read_register(SPIC1101_ADDR_MARCSTATE); + uint8_t sb=0; + sb = c1101_spi_read_register(CC1101_REG_RO_MARCSTATE); sb &= 0x1F; //debug start - /* char debug_sb[6]; */ + /* uint8_t debug_sb[6]; */ /* printf("c1101 MARCState:\r\n"); */ /* debug_sprint_int16hex(debug_sb, sb); */ /* printf("%s", debug_sb); */ @@ -544,7 +525,7 @@ char c1101_getMARCState(void) uint8_t c1101_getNumBytesInTXFifo(void) { - return c1101_spi_read_register(SPIC1101_ADDR_TXBYTES); + return c1101_spi_read_register(CC1101_REG_RO_TXBYTES); } @@ -555,7 +536,7 @@ bool c1101_waitUntilIDLEState(uint16_t timeout_ms) for (uint16_t c = 0; c < timeout_ms; c++) { sb = c1101_getStatus(); - if (SPIC1101_SB_IDLE(sb)) + if (CC1101_STATUS_IDLE(sb)) return true; _delay_ms(1); } @@ -597,23 +578,23 @@ bool c1101_writeFrequencyRegisters(uint32_t freq) if (! c1101_waitUntilIDLEState(2000)) //wait 2sec max return false; //programm frequency - c1101_spi_write_register(SPIC1101_ADDR_FREQ0, freq & 0xFF); - c1101_spi_write_register(SPIC1101_ADDR_FREQ1, (freq >> 8) & 0xFF); - c1101_spi_write_register(SPIC1101_ADDR_FREQ2, (freq >> 16) & 0x3F); + c1101_spi_write_register(CC1101_REG_RW_FREQ0, freq & 0xFF); + c1101_spi_write_register(CC1101_REG_RW_FREQ1, (freq >> 8) & 0xFF); + c1101_spi_write_register(CC1101_REG_RW_FREQ2, (freq >> 16) & 0x3F); //set channel 0 - c1101_spi_write_register(SPIC1101_ADDR_CHANNR, 0); + c1101_spi_write_register(CC1101_REG_RW_CHANNR, 0); return true; } uint32_t c1101_readFrequencyRegisters(void) { uint32_t freq = 0; - freq = ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ2)) & 0x3F; + freq = ((uint8_t) c1101_spi_read_register(CC1101_REG_RW_FREQ2)) & 0x3F; freq = freq << 8; - freq |= ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ1)); + freq |= ((uint8_t) c1101_spi_read_register(CC1101_REG_RW_FREQ1)); freq = freq << 8; - freq |= ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ0)); + freq |= ((uint8_t) c1101_spi_read_register(CC1101_REG_RW_FREQ0)); return freq; } @@ -621,7 +602,7 @@ uint32_t c1101_readFrequencyRegisters(void) // freq: desired_carrier_freq [Hz] *2^16 / f_XOSC bool c1101_setFrequency(uint32_t freq_hz) { - uint32_t freq = (uint32_t)((float)freq_hz / C1101_FREQ_TO_HZ); + uint32_t freq = (uint32_t)((float)freq_hz / CC1101_FREQ_CORR); if ( freq <= 0x3FFFFF) return c1101_writeFrequencyRegisters(freq); else @@ -632,7 +613,7 @@ bool c1101_setFrequency(uint32_t freq_hz) // freq: desired_carrier_freq [Hz] *2^16 / f_XOSC bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz) { - int32_t freq_change = (int32_t)((float)freq_change_hz / C1101_FREQ_TO_HZ); + int32_t freq_change = (int32_t)((float)freq_change_hz / CC1101_FREQ_CORR); int32_t freq = (int32_t) c1101_readFrequencyRegisters(); freq += freq_change; @@ -645,7 +626,7 @@ bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz) uint32_t c1101_getCurrentCarrierFrequencyHz(void) { - return (uint32_t)((float)c1101_readFrequencyRegisters() * C1101_FREQ_TO_HZ); + return (uint32_t)((float)c1101_readFrequencyRegisters() * CC1101_FREQ_CORR); } // if_freq: desired intermidiate rx frequency [Hz] *2^10 / f_XOSC @@ -656,22 +637,22 @@ bool c1101_setIFFrequency(uint32_t freq_hz) if (! c1101_waitUntilIDLEState(2000)) //wait 2sec max return false; - c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, if_freq & 0x1F); + c1101_spi_write_register(CC1101_REG_RW_FSCTRL1, if_freq & 0x1F); return true; } -bool c1101_transmitData(char *buffer, uint8_t len) +bool c1101_transmitData(uint8_t *buffer, uint8_t len) { //~ uint8_t debug_sb[6]; uint8_t num_written = 0; bool success = true; - //~ uint8_t mcsm1 = c1101_spi_read_register(SPIC1101_ADDR_MCSM1); + //~ uint8_t mcsm1 = c1101_spi_read_register(CC1101_REG_RW_MCSM1); //~ //configure state machine to automatically go to IDLE, once packet was transmitted //~ mcsm1 = (mcsm1 & 0b11111100) | 0b00; - //~ c1101_spi_write_register(SPIC1101_ADDR_MCSM1, 0x18); - //~ c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) + //~ c1101_spi_write_register(CC1101_REG_RW_MCSM1, 0x18); + //~ c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) // flush TX FIFO - c1101_spi_strobe_command(SPIC1101_ADDR_SFTX); + c1101_spi_strobe_command(CC1101_CMD_SFTX); //~ //fill buffer //~ num_written = c1101_spi_write_txfifo(buffer, len); @@ -691,8 +672,8 @@ bool c1101_transmitData(char *buffer, uint8_t len) //~ (debug_sb,255); //start transmitting - //num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX); - //~ num_written = hhd70_spi_exchange_byte(SPIC1101_ADDR_STX); + //num_written = c1101_spi_strobe_command(CC1101_CMD_STX); + //~ num_written = hhd70_spi_exchange_byte(CC1101_CMD_STX); //~ ((uint8_t*)"Strobe STX",255); //~ debug_sprint_int16hex(debug_sb, num_written); //~ (debug_sb,255); @@ -715,7 +696,7 @@ bool c1101_transmitData(char *buffer, uint8_t len) goto c1101_transmitData_cleanup; } //from state IDLE or RX go to TX - num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX); + num_written = c1101_spi_strobe_command(CC1101_CMD_STX); //~ ((uint8_t*)"TX2 num written",255); //~ debug_sprint_int16hex(debug_sb, num_written); @@ -742,10 +723,10 @@ bool c1101_transmitData(char *buffer, uint8_t len) return success; } -void c1101_transmitData_infPktMode(char *buffer, uint8_t len) +void c1101_transmitData_infPktMode(uint8_t *buffer, uint8_t len) { //in infinite Packet Mode, prepend length to buffer: - char *new_buffer = malloc(len+1); + uint8_t *new_buffer = malloc(len+1); new_buffer[0] = len; memcpy(new_buffer+1, buffer, len); //variable packet length: write length of packet to TX FIFO: @@ -756,7 +737,7 @@ void c1101_transmitData_infPktMode(char *buffer, uint8_t len) void c1101_recieveData(void) { uint8_t const max_len=255; - char recv_data[256]; + uint8_t recv_data[256]; uint8_t num_recv = 0; uint8_t num_recv_total = 0; uint8_t num_leave_in_fifo = 1; @@ -777,7 +758,7 @@ void c1101_recieveData(void) } //max returned: 64 bytes -int c1101_readRXFifo(char *buffer) +int c1101_readRXFifo(uint8_t *buffer) { //check RXBYTES.NUM_RXBYTES // never read more bytes than avaiblabe or we will read garbage |