diff options
Diffstat (limited to 'software/mpu/inc')
| -rw-r--r-- | software/mpu/inc/FreeRTOSConfig.h | 108 | ||||
| -rw-r--r-- | software/mpu/inc/Types.h | 33 | ||||
| -rw-r--r-- | software/mpu/inc/ssp.h | 112 |
3 files changed, 253 insertions, 0 deletions
diff --git a/software/mpu/inc/FreeRTOSConfig.h b/software/mpu/inc/FreeRTOSConfig.h new file mode 100644 index 0000000..5ddf25c --- /dev/null +++ b/software/mpu/inc/FreeRTOSConfig.h @@ -0,0 +1,108 @@ +/*
+ FreeRTOS V6.0.0 - Copyright (C) 2009 Real Time Engineers Ltd.
+
+ This file is part of the FreeRTOS distribution.
+
+ FreeRTOS is free software; you can redistribute it and/or modify it under
+ the terms of the GNU General Public License (version 2) as published by the
+ Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
+ ***NOTE*** The exception to the GPL is included to allow you to distribute
+ a combined work that includes FreeRTOS without being obliged to provide the
+ source code for proprietary components outside of the FreeRTOS kernel.
+ FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details. You should have received a copy of the GNU General Public
+ License and the FreeRTOS license exception along with FreeRTOS; if not it
+ can be viewed here: http://www.freertos.org/a00114.html and also obtained
+ by writing to Richard Barry, contact details for whom are available on the
+ FreeRTOS WEB site.
+
+ 1 tab == 4 spaces!
+
+ http://www.FreeRTOS.org - Documentation, latest information, license and
+ contact details.
+
+ http://www.SafeRTOS.com - A version that is certified for use in safety
+ critical systems.
+
+ http://www.OpenRTOS.com - Commercial support, development, porting,
+ licensing and training services.
+*/
+
+
+/******************************************************************************
+ See http://www.freertos.org/a00110.html for an explanation of the
+ definitions contained in this file.
+******************************************************************************/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include "LPC13xx.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *----------------------------------------------------------*/
+
+extern unsigned int SystemCoreClock;
+
+#define configUSE_PREEMPTION 1
+#define configUSE_IDLE_HOOK 0
+#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
+#define configUSE_TICK_HOOK 0
+#define configCPU_CLOCK_HZ ( ( unsigned long ) SystemCoreClock )
+#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
+#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 100 )
+#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 2 * 1024 ) )
+#define configMAX_TASK_NAME_LEN ( 12 )
+#define configUSE_TRACE_FACILITY 0
+#define configUSE_16_BIT_TICKS 0
+#define configIDLE_SHOULD_YIELD 0
+#define configUSE_CO_ROUTINES 0
+#define configUSE_MUTEXES 1
+
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+#define configUSE_COUNTING_SEMAPHORES 1
+#define configUSE_ALTERNATIVE_API 0
+#define configCHECK_FOR_STACK_OVERFLOW 0
+#define configUSE_RECURSIVE_MUTEXES 0
+#define configQUEUE_REGISTRY_SIZE 0
+#define configGENERATE_RUN_TIME_STATS 0
+#define configUSE_MALLOC_FAILED_HOOK 0
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet 1
+#define INCLUDE_uxTaskPriorityGet 1
+#define INCLUDE_vTaskDelete 1
+#define INCLUDE_vTaskCleanUpResources 0
+#define INCLUDE_vTaskSuspend 1
+#define INCLUDE_vTaskDelayUntil 1
+#define INCLUDE_vTaskDelay 1
+#define INCLUDE_uxTaskGetStackHighWaterMark 0
+
+/* Use the system definition, if there is one */
+#ifdef __NVIC_PRIO_BITS
+ #define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+ #define configPRIO_BITS 5 /* 32 priority levels */
+#endif
+
+/* The lowest priority. */
+#define configKERNEL_INTERRUPT_PRIORITY ( 31 << (8 - configPRIO_BITS) )
+/* Priority 5, or 160 as only the top three bits are implemented. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( 5 << (8 - configPRIO_BITS) )
+
+
+
+#endif /* FREERTOS_CONFIG_H */
+
diff --git a/software/mpu/inc/Types.h b/software/mpu/inc/Types.h new file mode 100644 index 0000000..501d359 --- /dev/null +++ b/software/mpu/inc/Types.h @@ -0,0 +1,33 @@ +#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+typedef enum
+{
+ STATUS_OK = 0x0U,
+ STATUS_ERROR_INIT,
+ STATUS_ERROR_SND,
+ STATUS_ERROR_RCV,
+ STATUS_ERROR_TIMEOUT
+}Status_t;
+
+typedef enum
+{
+ Sender_Kernel = 0x0,
+ Sender_Camera,
+ Sender_Spi,
+ Sender_LightSens
+}Sender_t;
+
+typedef struct
+{
+ void *pData;
+ Sender_t Sender;
+}Message_t;
+
+typedef struct
+{
+ xTaskHandle *pxTask_Lightsens;
+ xQueueHandle *pxQueue;
+}Task_Param_t;
+
diff --git a/software/mpu/inc/ssp.h b/software/mpu/inc/ssp.h new file mode 100644 index 0000000..e910a4d --- /dev/null +++ b/software/mpu/inc/ssp.h @@ -0,0 +1,112 @@ +/*****************************************************************************
+ * ssp.h: Header file for NXP LPC134x Family Microprocessors
+ *
+ * Copyright(C) 2006, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2006.07.19 ver 1.00 Preliminary version, first Release
+ *
+******************************************************************************/
+#ifndef __SSP_H__
+#define __SSP_H__
+
+/* There are there modes in SSP: loopback, master or slave. */
+/* Here are the combination of all the tests.
+(1) LOOPBACK test: LOOPBACK_MODE=1, TX_RX_ONLY=0, USE_CS=1;
+(2) Serial EEPROM test: LOOPBACK_MODE=0, TX_RX_ONLY=0, USE_CS=0; (default)
+(3) TX(Master) Only: LOOPBACK_MODE=0, SSP_SLAVE=0, TX_RX_ONLY=1, USE_CS=1;
+(4) RX(Slave) Only: LOOPBACK_MODE=0, SSP_SLAVE=1, TX_RX_ONLY=0, USE_CS=1 */
+
+#define LOOPBACK_MODE 1 /* 1 is loopback, 0 is normal operation. */
+#define SSP_SLAVE 0 /* 1 is SLAVE mode, 0 is master mode */
+#define TX_RX_ONLY 0 /* 1 is TX or RX only depending on SSP_SLAVE
+ flag, 0 is either loopback mode or communicate
+ with a serial EEPROM. */
+
+/* if USE_CS is zero, set SSEL as GPIO that you have total control of the sequence */
+/* When test serial SEEPROM(LOOPBACK_MODE=0, TX_RX_ONLY=0), set USE_CS to 0. */
+/* When LOOPBACK_MODE=1 or TX_RX_ONLY=1, set USE_CS to 1. */
+
+#define USE_CS 1
+#define SSP_DEBUG 0
+
+/* SPI read and write buffer size */
+#define SSP_BUFSIZE 16
+#define FIFOSIZE 8
+
+#define DELAY_COUNT 10
+#define MAX_TIMEOUT 0xFF
+
+/* Port0.2 is the SSP select pin */
+#define SSP0_SEL (1 << 2)
+
+/* SSP Status register */
+#define SSPSR_TFE (1 << 0)
+#define SSPSR_TNF (1 << 1)
+#define SSPSR_RNE (1 << 2)
+#define SSPSR_RFF (1 << 3)
+#define SSPSR_BSY (1 << 4)
+
+/* SSP CR0 register */
+#define SSPCR0_DSS (1 << 0)
+#define SSPCR0_FRF (1 << 4)
+#define SSPCR0_SPO (1 << 6)
+#define SSPCR0_SPH (1 << 7)
+#define SSPCR0_SCR (1 << 8)
+
+/* SSP CR1 register */
+#define SSPCR1_LBM (1 << 0)
+#define SSPCR1_SSE (1 << 1)
+#define SSPCR1_MS (1 << 2)
+#define SSPCR1_SOD (1 << 3)
+
+/* SSP Interrupt Mask Set/Clear register */
+#define SSPIMSC_RORIM (1 << 0)
+#define SSPIMSC_RTIM (1 << 1)
+#define SSPIMSC_RXIM (1 << 2)
+#define SSPIMSC_TXIM (1 << 3)
+
+/* SSP0 Interrupt Status register */
+#define SSPRIS_RORRIS (1 << 0)
+#define SSPRIS_RTRIS (1 << 1)
+#define SSPRIS_RXRIS (1 << 2)
+#define SSPRIS_TXRIS (1 << 3)
+
+/* SSP0 Masked Interrupt register */
+#define SSPMIS_RORMIS (1 << 0)
+#define SSPMIS_RTMIS (1 << 1)
+#define SSPMIS_RXMIS (1 << 2)
+#define SSPMIS_TXMIS (1 << 3)
+
+/* SSP0 Interrupt clear register */
+#define SSPICR_RORIC (1 << 0)
+#define SSPICR_RTIC (1 << 1)
+
+/* ATMEL SEEPROM command set */
+#define WREN 0x06 /* MSB A8 is set to 0, simplifying test */
+#define WRDI 0x04
+#define RDSR 0x05
+#define WRSR 0x01
+#define READ 0x03
+#define WRITE 0x02
+
+/* RDSR status bit definition */
+#define RDSR_RDY 0x01
+#define RDSR_WEN 0x02
+
+/* If RX_INTERRUPT is enabled, the SSP RX will be handled in the ISR
+SSPReceive() will not be needed. */
+extern void SSP_IRQHandler (void);
+extern void SSPInit( void );
+extern void SSPSend( uint8_t *Buf, uint32_t Length );
+extern void SSPReceive( uint8_t *buf, uint32_t Length );
+
+extern uint8_t src_addr[SSP_BUFSIZE];
+extern uint8_t dest_addr[SSP_BUFSIZE];
+extern void LoopbackTest( void );
+#endif /* __SSP_H__ */
+/*****************************************************************************
+** End Of File
+******************************************************************************/
+
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