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authorBernhard Tittelbach <xro@realraum.at>2012-05-19 04:42:02 +0000
committerBernhard Tittelbach <xro@realraum.at>2012-05-19 04:42:02 +0000
commitc464f9a79a3d7b6a3ddb520636595febe9783759 (patch)
treec995e76b8d6546eef48483bc6466629650a716be /software
parentmore TX test, Carrier is there, but FIFO not emptied (diff)
variable packet mode works, where infinite packet mode apparently doesn't
git-svn-id: https://svn.spreadspace.org/mur.sat@434 7de4ea59-55d0-425e-a1af-a3118ea81d4c
Diffstat (limited to 'software')
-rw-r--r--software/hhd70dongle/c1101lib.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/software/hhd70dongle/c1101lib.c b/software/hhd70dongle/c1101lib.c
index a80fa49..06c825c 100644
--- a/software/hhd70dongle/c1101lib.c
+++ b/software/hhd70dongle/c1101lib.c
@@ -192,8 +192,8 @@ void c1101_init(void)
// pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx)
spi_c1101_write_register(SPIC1101_ADDR_FIFOTHR, 2);
// PKTCTRL0 Packet Automation Control
- spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode
- //spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+ //spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode
+ spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet
// FSCTRL1 Frequency Synthesizer Control
spi_c1101_write_register(SPIC1101_ADDR_FSCTRL1, 0x06);
@@ -338,12 +338,16 @@ void c1101_transmitData(char *buffer, unsigned int len)
//configure state machine to automatically go to IDLE, once packet was transmitted
mcsm1 = (mcsm1 & 0b11111100) | 0b00;
spi_c1101_write_register(SPIC1101_ADDR_MCSM1, 0x18);
- // flush TX Buffer
+ spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+ // flush TX FIFO
num_written = spi_c1101_strobe_command(SPIC1101_ADDR_SFTX);
usb_rawhid_send((uint8_t*)"Flush TX Fifo",255);
debug_sprint_int16hex(debug_sb, num_written);
usb_rawhid_send(debug_sb,255);
+ num_written = (uint8_t) len;
+ //variable packet length: write length of packet to TX FIFO:
+ spi_c1101_write_txfifo((char*) &num_written, 1);
//~ //fill buffer
//~ num_written = spi_c1101_write_txfifo(buffer, len);