blob: 618c5811d3b5be8f6a74e8c3549c2c978f09046c (
plain) (
blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
|
/*
*
* mur.sat
*
* Somewhen in the year 2012, mur.at will have a nano satellite launched
* into a low earth orbit (310 km above the surface of our planet). The
* satellite itself is a TubeSat personal satellite kit, developed and
* launched by interorbital systems. mur.sat is a joint venture of mur.at,
* ESC im Labor and realraum.
*
* Please visit the project hompage at sat.mur.at for further information.
*
*
* Copyright (C) 2011 Christian Pointner <equinox@mur.at>
*
* This file is part of mur.sat.
*
* mur.sat is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* any later version.
*
* mur.sat is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with mur.sat. If not, see <http://www.gnu.org/licenses/>.
*
*/
#include "avr/io.h"
#include "spi.h"
#define SPI_DDR DDRB
#define SPI_PORT PORTB
#define SPI_PINB_REG PINB
#define CS 0
#define SCK 1
#define MOSI 2
#define MISO 3
#define GDO2 4
#define GDO0 5
#define RE 6
#define TE 7
void spi_init(void)
{
//configure Direction of SS / PB0 , MOSI and SCLK as Output to drive CS of CC1101
DDRB = (1<<DDB0) | (1<<DDB1) | (1<<DDB2);
SPI_PORT = 0;
SPI_DDR = (1<<MOSI)|(1<<SCK)|(1<<CS);
SPCR = (1<<SPE)|(1<<MSTR);
// SPSR = (0<<SPI2X) // f_osc/4
// SPSR = (1<<SPI2X) // f_osc/2
// SPSR = (1<<SPI2X); (4MHz vs. 8MHz)
}
//synchronous
void spi_write_byte(char byte)
{
SPDR = byte; //Load byte to Data register
while(!(SPSR & (1<<SPIF))); // Wait for transmission complete
}
void spi_write(char* data, unsigned int len)
{
//enable SS of CC1101
PORTB |= (1<<CS);
for (unsigned int c=0; c++; c<len)
spi_write_byte(data[c])
//disable SS of CC1101
PORTB &= ~(1<<CS);
}
void spi_read(unsigned int maxlen, char* data)
{
PORTB |= (1<<CS);
while(SPI_PINB_REG & (1<<MISO)); /* wait for CC1101 to get ready... */
SPDR = 0x80;
unsigned int len = 0;
while(len < maxlen && !(SPSR & (1<<SPIF)))
{
data[len++]=SPSR
}
PORTB &= ~(1<<CS);
}
//~ void SPI_interrupt(void) __interrupt (0x0053) __using (1)
//~ {
//~ //P1_0=0;
//~ switch ( SPSCR ) /* read and clear spi status register */
//~ {
//~ case 0x80:
//~ serial_data=SPDAT; /* read receive data */
//~ transmit_completed=1;/* set software flag */
//~ break;
//~ case 0x10:
//~ /* put here for mode fault tasking */
//~ break;
//~ case 0x40:
//~ /* put here for overrun tasking */
//~ break;
//~ }
//~ }
|