path: root/software/hhd70dongle/c1101lib.c

/*
 *
 *  mur.sat
 *
 *  Somewhen in the year 2012, mur.at will have a nano satellite launched
 *  into a low earth orbit (310 km above the surface of our planet). The
 *  satellite itself is a TubeSat personal satellite kit, developed and
 *  launched by interorbital systems. mur.sat is a joint venture of mur.at,
 *  ESC im Labor and realraum.
 *
 *  Please visit the project hompage at sat.mur.at for further information.
 *
 *
 *  Copyright (C) 2012 Bernhard Tittelbach <xro@realraum.at>
 *
 *  This file is part of mur.sat.
 *
 *  mur.sat is free software: you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, either version 3 of the License, or
 *  any later version.
 *
 *  mur.sat is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with mur.sat. If not, see <http://www.gnu.org/licenses/>.
 *
 */
#include <avr/io.h>
#include <util/delay.h>

#include "c1101lib.h"
#include "hhd70.h"
#include "util.h"

/**** Helper Functions ****/

#define SPIC1101_MAX_WAIT 21



/* ######          ######
             LUFA Library
     Copyright (C) Dean Camera, 2012.

  dean [at] fourwalledcubicle [dot] com
           www.lufa-lib.org
*/
//#include <LUFA/Drivers/Misc/RingBuffer.h>
#include <LUFA/Drivers/USB/USB.h>

   /* Global I/O Buffers: */
//static RingBuffer_t SPItoUSB_Buffer;
//static uint8_t      SPItoUSB_Buffer_Data[8];

/** LUFA CDC Class driver interface configuration and state information. This structure is
 *  passed to all CDC Class driver functions, so that multiple instances of the same class
 *  within a device can be differentiated from one another.
 */
extern USB_ClassInfo_CDC_Device_t VirtualSerial_CDC_Interface;
/* ###### end LUFA CDC-ACM specific definitions ###### */



int16_t c1101_spi_write_byte_ok_get_status(char data)
{
    //~ uint8_t debug_sb[6];
    char sb;
    unsigned int attempts = 0;
    do
    {
        sb = hhd70_spi_exchange_byte(data);
        //Note: content of returned StatusByte is actually context depenedant on sent command
        //            i.e. we won't get Fifo Byte count or overflow status on normal command and so on
        //            e.g. we only get TX Fifo Free Byte count while writing to TX Fifo
        //            thus it makes sense to only check for CHIP_RDY here
        //~ ((uint8_t*)"spi byte exchanged ",255);
        //~ debug_sprint_int16hex(debug_sb, sb);
        //~ (debug_sb,255);
        if (attempts++ > SPIC1101_MAX_WAIT)
            return -1;
    } while ( SPIC1101_SB_CHIP_NOT_RDY(sb) );
    return sb;
}

int16_t c1101_spi_strobe_command(char address)
{
    char rbyte;
    if (address < 0x30)
        return -1;
    hhd70_spi_cs_enable();
    hhd70_c1101_wait_chip_rdy();
    //POST DEBUG: don't return anything
    rbyte = c1101_spi_write_byte_ok_get_status(address);
    if (rbyte < 0)
        return -1;
    hhd70_spi_cs_disable();
    return rbyte;
}

// note addresses range from 0x00 to 0x2F for normal registers and 0xF0 to 0xFD for special status registers
int16_t c1101_spi_read_register(char address)
{
    char rbyte;
    if (address < 0x30)
        address |= 0x80;
    else
        address |= 0xC0;
    hhd70_spi_cs_enable();
    hhd70_c1101_wait_chip_rdy();
    if (c1101_spi_write_byte_ok_get_status(address) < 0)
        return -1;
    rbyte = hhd70_spi_read_byte();
    hhd70_spi_cs_disable();
    return rbyte;
}

// note addresses range from 0x00 to 0x2F for normal registers
int16_t c1101_spi_write_register(char address, char byte)
{
    hhd70_spi_cs_enable();
    hhd70_c1101_wait_chip_rdy();
    if (c1101_spi_write_byte_ok_get_status(address & 0x3F) < 0)
        return -1;
    _delay_ms(2);
    if (c1101_spi_write_byte_ok_get_status(byte) < 0)
        return -1;
    hhd70_spi_cs_disable();
    return 1;
}

void c1101_spi_dump_registers_to_usb(void)
{
    int c = 0;
    char debug_sb[6];
    hhd70_spi_cs_enable();
    hhd70_c1101_wait_chip_rdy();
    if (c1101_spi_write_byte_ok_get_status(0xC0) < 0)
        return;
    CDC_Device_SendString(&VirtualSerial_CDC_Interface,"dump all 46 registers:");
    for (c=0; c<47; c++)
    {
        debug_sprint_int16hex(debug_sb, hhd70_spi_read_byte());
        CDC_Device_SendString(&VirtualSerial_CDC_Interface,  debug_sb);
    }
    hhd70_spi_cs_disable();
}

int c1101_spi_read_rxfifo(int leave_num_bytes, char *buffer, int maxlen)
{
    int num_read = 0;
    uint8_t num_available = 0;
    hhd70_spi_cs_enable();
    hhd70_c1101_wait_chip_rdy();
    if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_RXBYTES) < 0)
        return -1;
    num_available = hhd70_spi_read_byte();
    if (num_available == 0)
        return 0;
    if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST) < 0)
        return -1;
    while (maxlen--  > 0 && num_available - num_read > leave_num_bytes)
    {
        buffer[num_read++] = hhd70_spi_read_byte();
    }
    hhd70_spi_cs_disable();
    return num_read;
}

//note: currently this function reads at most 15 bytes
int c1101_spi_read_rxfifo_max15(int leave_num_bytes, char *buffer, int maxlen)
{
    int16_t sb;
    int num_read = 0;
    hhd70_spi_cs_enable();
    hhd70_c1101_wait_chip_rdy();
    sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST);
    if (sb < 0)
        return -1;
    //note if SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb)  == 15 then 15 or more bytes are available
    while (maxlen--  > 0 && SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) - num_read > leave_num_bytes)
    {
        //hope this works !!
        buffer[num_read++] = hhd70_spi_read_byte();
    }
    hhd70_spi_cs_disable();
    return num_read;
}

//note: always check if num_written returned == len given
int c1101_spi_write_txfifo(char *buffer, int len)
{
    char sb;
    int num_written = 0;
    hhd70_spi_cs_enable();
    hhd70_c1101_wait_chip_rdy();
    sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_WRITE_BURST);
    if (sb < 0)
        return -1;
    while (len-- > 0 && SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) > 2)
    {
        sb = c1101_spi_write_byte_ok_get_status(buffer[num_written++]);
    }
    hhd70_spi_cs_disable();
    return num_written;
}



/**** External Functions ****/

void c1101_init(void)
{
    //reset C1101
    c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
    _delay_ms(100);
    //flush FIFOs
    c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
    c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
    //dump pre-init default values to usb
    c1101_spi_dump_registers_to_usb();
    //enable analog temperature sensor on GDO0
    c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x80);
    //enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO)
    c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0);
    // FIFOTHR       RX FIFO and TX FIFO Thresholds
    // pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx)
    c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 2);
    // PKTCTRL0      Packet Automation Control
    //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode
    c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
    c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet
    // FSCTRL1       Frequency Synthesizer Control
    c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, 0x06);
    // FREQn         Frequency Control Words
    c1101_spi_write_register(SPIC1101_ADDR_FREQ2, 0x10); //should be 435.125 mhz
    c1101_spi_write_register(SPIC1101_ADDR_FREQ1, 0xBF);
    c1101_spi_write_register(SPIC1101_ADDR_FREQ0, 0xEF);
    c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, 0); //frequency offset
    // MDMCFGn       Modem Configuration
    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4, 0xF8);
    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3, 0x83);
    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2, 0x12); //gfsk, 15/16 sync word
    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG1, 0x00);
    //Sync Word
    c1101_spi_write_register(SPIC1101_ADDR_SYNC1, 0x21);
    c1101_spi_write_register(SPIC1101_ADDR_SYNC0, 0x42);
    // DEVIATN       Modem Deviation Setting
    c1101_spi_write_register(SPIC1101_ADDR_DEVIATN, 0x07);
    // MCSM0         Main Radio Control State Machine Configuration
    c1101_spi_write_register(SPIC1101_ADDR_MCSM0, 0x18);
    c1101_spi_write_register(SPIC1101_ADDR_MCSM1, 0b00111100);  // State RX after recieving packet->  stay in RX; State TX after sending packet -> IDLE
    // FOCCFG        Frequency Offset Compensation Configuration
    c1101_spi_write_register(SPIC1101_ADDR_FOCCFG, 0x16);
    // WORCTRL       Wake On Radio Control
    c1101_spi_write_register(SPIC1101_ADDR_WORCTRL, 0xFB);
    // FSCALn        Frequency Synthesizer Calibration
    c1101_spi_write_register(SPIC1101_ADDR_FSCAL3, 0xE9);
    c1101_spi_write_register(SPIC1101_ADDR_FSCAL2, 0x2A);
    c1101_spi_write_register(SPIC1101_ADDR_FSCAL1, 0x00);
    c1101_spi_write_register(SPIC1101_ADDR_FSCAL0, 0x1F);

    // note: for now: assume f_xosc to be 26 Mhz
    // for ~433.125 Mhz -> freq = 1091741, freq_offset = 0
    //c1101_setFrequency(1091741,0,15);
}

//f_XOSC = 26Mhz
// freq:            desired_carrier_freq [Hz] *2^16 / f_XOSC
// freq_offset:     desired frequency offset [Hz] *2^14 / f_XOSC
// if_freq:         desired intermidiate rx frequency [Hz] *2^10 / f_XOSC
void c1101_setFrequency(uint32_t freq, uint8_t freq_offset, uint8_t if_freq)
{
    //make sure we are in idle mode
    char sb=0;
    do
    {
        sb = c1101_getStatus();
    } while (! (SPIC1101_SB_IDLE(sb)));
    //programm frequency
    c1101_spi_write_register(SPIC1101_ADDR_FREQ0, freq & 0xFF);
    c1101_spi_write_register(SPIC1101_ADDR_FREQ1, (freq >> 8) & 0xFF);
    c1101_spi_write_register(SPIC1101_ADDR_FREQ2, (freq >> 16) & 0x3F);

    //set frequency offset
    c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, freq_offset);
    //c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, if_freq & 0x1F);

    //set channel 0
    c1101_spi_write_register(SPIC1101_ADDR_CHANNR, 0);
}

char c1101_putToSleep(void)
{
    return c1101_spi_strobe_command(SPIC1101_ADDR_SPWD);
}


uint16_t c1101_measureTemp(void)
{
    uint16_t temp;
    char ptest_value=0x7F;
    ptest_value = c1101_spi_read_register(SPIC1101_ADDR_PTEST);
    c1101_spi_write_register(SPIC1101_ADDR_PTEST, 0xBF);
    _delay_ms(5);
    temp = adc_read(ADCMUX_INTERNALTEMP);
    c1101_spi_write_register(SPIC1101_ADDR_PTEST, ptest_value);
    return temp;
}

void c1101_handleStatusByte(char sb)
{
    //on RXFifo Overflow, Flush RX Fifo
    if (SPIC1101_SB_RXFIFO_OVERFLOW(sb))
    {
        c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
        CDC_Device_SendString(&VirtualSerial_CDC_Interface,"RX fifo flushed");
    }
    //on TXFifo Overflow, Flush TX Fifo
    if (SPIC1101_SB_TXFIFO_OVERFLOW(sb))
    {
        c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
        CDC_Device_SendString(&VirtualSerial_CDC_Interface,"TX fifo flushed");
    }
}

char c1101_getStatus(void)
{
    char sb=0;
    hhd70_spi_cs_enable();
    hhd70_c1101_wait_chip_rdy();
    sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_SNOP);
    hhd70_spi_cs_disable();
    //debug start
    char debug_sb[6];
    CDC_Device_SendString(&VirtualSerial_CDC_Interface,"c1101 status:");
    debug_sprint_int16hex(debug_sb, sb);
    CDC_Device_SendString(&VirtualSerial_CDC_Interface,debug_sb);
    //debug end
    c1101_handleStatusByte(sb);
    return sb;
}

char c1101_getMARCState(void)
{
    char sb=0;
    sb = c1101_spi_read_register(SPIC1101_ADDR_MARCSTATE);
    sb &= 0x1F;
    //debug start
    char debug_sb[6];
    CDC_Device_SendString(&VirtualSerial_CDC_Interface,"c1101 MARCSate:");
    debug_sprint_int16hex(debug_sb, sb);
    CDC_Device_SendString(&VirtualSerial_CDC_Interface,debug_sb);
    //debug end
    return sb;
}

uint8_t c1101_getNumBytesInTXFifo(void)
{
    return c1101_spi_read_register(SPIC1101_ADDR_TXBYTES);
}

void c1101_transmitData(char *buffer, unsigned int len)
{
    //~ uint8_t debug_sb[6];
    uint8_t num_written = 0;
    //~ uint8_t mcsm1 = c1101_spi_read_register(SPIC1101_ADDR_MCSM1);
    //~ //configure state machine to automatically go to IDLE, once packet was transmitted
    //~ mcsm1 = (mcsm1 & 0b11111100) | 0b00;
    //~ c1101_spi_write_register(SPIC1101_ADDR_MCSM1, 0x18);
    //~ c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
    // flush TX FIFO
    num_written = c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);

    num_written = (uint8_t) len;
    //variable packet length: write length of packet to TX FIFO:
    c1101_spi_write_txfifo((char*) &num_written, 1);

    //~ //fill buffer
    //~ num_written = c1101_spi_write_txfifo(buffer, len);
    //~ buffer += num_written;
    //~ len -= num_written;

    //~ ((uint8_t*)"TX num written",255);
    //~ debug_sprint_int16hex(debug_sb, num_written);
    //~ (debug_sb,255);
    //~ ((uint8_t*)"TX len",255);
    //~ debug_sprint_int16hex(debug_sb, len);
    //~ (debug_sb,255);

    //~ c1101_getStatus();
    //~ ((uint8_t*)"TX bytes",255);
    //~ debug_sprint_int16hex(debug_sb, c1101_getNumBytesInTXFifo());
    //~ (debug_sb,255);

    //start transmitting
    //num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX);
    //~ num_written = hhd70_spi_exchange_byte(SPIC1101_ADDR_STX);
    //~ ((uint8_t*)"Strobe STX",255);
    //~ debug_sprint_int16hex(debug_sb, num_written);
    //~ (debug_sb,255);

    //enable Power Amplifier
    hhd70_palna_txmode();

    //keep buffer filled
    uint8_t c1101_state=0;
    do
    {
        c1101_getStatus();
        num_written = c1101_spi_write_txfifo(buffer,  len );
        buffer += num_written;
        len -= num_written;
        c1101_state = c1101_getMARCState();
        if (c1101_state == 1 || (c1101_state >= 13  && c1101_state <= 15))
        {
            //from state IDLE or RX go to TX
            num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX);
            //~ ((uint8_t*)"Strobe STX",255);
            //~ debug_sprint_int16hex(debug_sb, num_written);
            //~ (debug_sb,255);
        }
        //~ ((uint8_t*)"TX2 num written",255);
        //~ debug_sprint_int16hex(debug_sb, num_written);
        //~ (debug_sb,255);
        //~ ((uint8_t*)"TX2 len",255);
        //~ debug_sprint_int16hex(debug_sb, len);
        //~ (debug_sb,255);
        //~ ((uint8_t*)"TX2 bytes",255);
        //~ debug_sprint_int16hex(debug_sb, c1101_getNumBytesInTXFifo());
        //~ (debug_sb,255);
    } while (len > 0);

    //disable Power Amplifier
    //FIXME, instead use PTT function of GPO0 -> interrupt handler -> toggle rx/tx
    //wait until RX finished
    do
    {
        c1101_state = c1101_getMARCState();
        _delay_ms(1);
    }
    while (c1101_state == 19 || c1101_state == 20);
    hhd70_palna_rxmode();
}

void c1101_recieveData(void)
{
    uint8_t const max_len=255;
    char recv_data[256];
    uint8_t num_recv = 0;
    uint8_t num_recv_total = 0;
    uint8_t num_leave_in_fifo = 1;
    do
    {
        num_recv = c1101_spi_read_rxfifo( num_leave_in_fifo, recv_data+num_recv_total, max_len - num_recv_total);
        num_recv_total += num_recv;

        //variable packet length:
        //don't read last byte in fifo unless packet has finished receiving
        num_leave_in_fifo = (recv_data[0] - num_recv_total < 64)? 0 : 1;
    } while (num_recv > 0);
    recv_data[num_recv_total]=0;
    CDC_Device_SendString(&VirtualSerial_CDC_Interface,"RX: Data Recieved:");
    CDC_Device_SendString(&VirtualSerial_CDC_Interface,recv_data);
    c1101_getStatus(); // get status and handle possiblble RX Fifo Overflow
}

//max returned: 64 bytes
int c1101_readRXFifo(char *buffer)
{
    //check RXBYTES.NUM_RXBYTES
    // never read more bytes than avaiblabe or we will read garbage

    //note: if RX transmission fills fifo buffer at exact same time as last RX Fifo Bit is read via SPI, Fifo Pointer will not be properly updated
    //            and last read byte will be duplicated.
    // thus: don't last avialable FIFO Bytes unless we can be sure that it will be the last byte of a packet and we can be sure that a following duplicated byte is actually an Fifo duplication and not an actually recieved byte !

    return 0;
}