diff options
Diffstat (limited to 'software/mpu/src/ssp')
| -rw-r--r-- | software/mpu/src/ssp/ssp.c | 224 | ||||
| -rw-r--r-- | software/mpu/src/ssp/ssp.h | 109 | ||||
| -rw-r--r-- | software/mpu/src/ssp/ssptest.c | 190 |
3 files changed, 523 insertions, 0 deletions
diff --git a/software/mpu/src/ssp/ssp.c b/software/mpu/src/ssp/ssp.c new file mode 100644 index 0000000..edda1fd --- /dev/null +++ b/software/mpu/src/ssp/ssp.c @@ -0,0 +1,224 @@ +/*****************************************************************************
+ * ssp.c: SSP C file for NXP LPC13xx Family Microprocessors
+ *
+ * Copyright(C) 2008, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2008.07.20 ver 1.00 Preliminary version, first Release
+ *
+*****************************************************************************/
+#include "LPC13xx.h" /* LPC13xx Peripheral Registers */
+#include "../gpio/gpio.h"
+#include "ssp.h"
+
+/* statistics of all the interrupts */
+volatile uint32_t interruptRxStat = 0;
+volatile uint32_t interruptOverRunStat = 0;
+volatile uint32_t interruptRxTimeoutStat = 0;
+
+/*****************************************************************************
+** Function name: SSP_IRQHandler
+**
+** Descriptions: SSP port is used for SPI communication.
+** SSP interrupt handler
+** The algorithm is, if RXFIFO is at least half full,
+** start receive until it's empty; if TXFIFO is at least
+** half empty, start transmit until it's full.
+** This will maximize the use of both FIFOs and performance.
+**
+** parameters: None
+** Returned value: None
+**
+*****************************************************************************/
+void SSP_IRQHandler(void)
+{
+ uint32_t regValue;
+
+ regValue = LPC_SSP->MIS;
+ if ( regValue & SSPMIS_RORMIS ) /* Receive overrun interrupt */
+ {
+ interruptOverRunStat++;
+ LPC_SSP->ICR = SSPICR_RORIC; /* clear interrupt */
+ }
+ if ( regValue & SSPMIS_RTMIS ) /* Receive timeout interrupt */
+ {
+ interruptRxTimeoutStat++;
+ LPC_SSP->ICR = SSPICR_RTIC; /* clear interrupt */
+ }
+
+ /* please be aware that, in main and ISR, CurrentRxIndex and CurrentTxIndex
+ are shared as global variables. It may create some race condition that main
+ and ISR manipulate these variables at the same time. SSPSR_BSY checking (polling)
+ in both main and ISR could prevent this kind of race condition */
+ if ( regValue & SSPMIS_RXMIS ) /* Rx at least half full */
+ {
+ interruptRxStat++; /* receive until it's empty */
+ }
+ return;
+}
+
+/*****************************************************************************
+** Function name: SSPInit
+**
+** Descriptions: SSP port initialization routine
+**
+** parameters: None
+** Returned value: None
+**
+*****************************************************************************/
+void SSPInit( void )
+{
+ uint8_t i, Dummy=Dummy;
+
+ LPC_SYSCON->PRESETCTRL |= (0x1<<0);
+ LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11);
+ LPC_SYSCON->SSPCLKDIV = 0x02; /* Divided by 2 */
+ LPC_IOCON->PIO0_8 &= ~0x07; /* SSP I/O config */
+ LPC_IOCON->PIO0_8 |= 0x01; /* SSP MISO */
+ LPC_IOCON->PIO0_9 &= ~0x07;
+ LPC_IOCON->PIO0_9 |= 0x01; /* SSP MOSI */
+#ifdef __JTAG_DISABLED
+ LPC_IOCON->SCKLOC = 0x00;
+ LPC_IOCON->JTAG_TCK_PIO0_10 &= ~0x07;
+ LPC_IOCON->JTAG_TCK_PIO0_10 |= 0x02; /* SSP CLK */
+#endif
+
+#if 1
+ /* On HummingBird 1(HB1), SSP CLK can be routed to different pins,
+ other than JTAG TCK, it's either P2.11 func. 1 or P0.6 func. 2. */
+ LPC_IOCON->SCKLOC = 0x01;
+ LPC_IOCON->PIO2_11 = 0x01;/* P2.11 function 1 is SSP clock, need to combined
+ with IOCONSCKLOC register setting */
+#else
+ LPC_IOCON->SCKLOC = 0x02;
+ LPC_IOCON->PIO0_6 = 0x02; /* P0.6 function 2 is SSP clock, need to combined
+ with IOCONSCKLOC register setting */
+#endif
+
+#if USE_CS
+ LPC_IOCON->PIO0_2 &= ~0x07;
+ LPC_IOCON->PIO0_2 |= 0x01; /* SSP SSEL */
+#else
+ LPC_IOCON->PIO0_2 &= ~0x07; /* SSP SSEL is a GPIO pin */
+ /* port0, bit 2 is set to GPIO output and high */
+ GPIOSetDir( PORT0, 2, 1 );
+ GPIOSetValue( PORT0, 2, 1 );
+#endif
+
+ /* Set DSS data to 8-bit, Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */
+ LPC_SSP->CR0 = 0x0707;
+
+ /* SSPCPSR clock prescale register, master mode, minimum divisor is 0x02 */
+ LPC_SSP->CPSR = 0x2;
+
+ for ( i = 0; i < FIFOSIZE; i++ )
+ {
+ Dummy = LPC_SSP->DR; /* clear the RxFIFO */
+ }
+
+ /* Enable the SSP Interrupt */
+ NVIC_EnableIRQ(SSP_IRQn);
+
+ /* Device select as master, SSP Enabled */
+#if LOOPBACK_MODE
+ LPC_SSP->CR1 = SSPCR1_LBM | SSPCR1_SSE;
+#else
+#if SSP_SLAVE
+ /* Slave mode */
+ if ( LPC_SSP->CR1 & SSPCR1_SSE )
+ {
+ /* The slave bit can't be set until SSE bit is zero. */
+ LPC_SSP->CR1 &= ~SSPCR1_SSE;
+ }
+ LPC_SSP->CR1 = SSPCR1_MS; /* Enable slave bit first */
+ LPC_SSP->CR1 |= SSPCR1_SSE; /* Enable SSP */
+#else
+ /* Master mode */
+ LPC_SSP->CR1 = SSPCR1_SSE;
+#endif
+#endif
+ /* Set SSPINMS registers to enable interrupts */
+ /* enable all error related interrupts */
+ LPC_SSP->IMSC = SSPIMSC_RORIM | SSPIMSC_RTIM;
+ return;
+}
+
+/*****************************************************************************
+** Function name: SSPSend
+**
+** Descriptions: Send a block of data to the SSP port, the
+** first parameter is the buffer pointer, the 2nd
+** parameter is the block length.
+**
+** parameters: buffer pointer, and the block length
+** Returned value: None
+**
+*****************************************************************************/
+void SSPSend( uint8_t *buf, uint32_t Length )
+{
+ uint32_t i;
+ uint8_t Dummy = Dummy;
+
+ for ( i = 0; i < Length; i++ )
+ {
+ /* Move on only if NOT busy and TX FIFO not full. */
+ while ( (LPC_SSP->SR & (SSPSR_TNF|SSPSR_BSY)) != SSPSR_TNF );
+ LPC_SSP->DR = *buf;
+ buf++;
+#if !LOOPBACK_MODE
+ while ( (LPC_SSP->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
+ /* Whenever a byte is written, MISO FIFO counter increments, Clear FIFO
+ on MISO. Otherwise, when SSP0Receive() is called, previous data byte
+ is left in the FIFO. */
+ Dummy = LPC_SSP->DR;
+#else
+ /* Wait until the Busy bit is cleared. */
+ while ( LPC_SSP->SR & SSPSR_BSY );
+#endif
+ }
+ return;
+}
+
+/*****************************************************************************
+** Function name: SSPReceive
+** Descriptions: the module will receive a block of data from
+** the SSP, the 2nd parameter is the block
+** length.
+** parameters: buffer pointer, and block length
+** Returned value: None
+**
+*****************************************************************************/
+void SSPReceive( uint8_t *buf, uint32_t Length )
+{
+ uint32_t i;
+
+ for ( i = 0; i < Length; i++ )
+ {
+ /* As long as Receive FIFO is not empty, I can always receive. */
+ /* If it's a loopback test, clock is shared for both TX and RX,
+ no need to write dummy byte to get clock to get the data */
+ /* if it's a peer-to-peer communication, SSPDR needs to be written
+ before a read can take place. */
+#if !LOOPBACK_MODE
+#if SSP_SLAVE
+ while ( !(LPC_SSP->SR & SSPSR_RNE) );
+#else
+ LPC_SSP->DR = 0xFF;
+ /* Wait until the Busy bit is cleared */
+ while ( (LPC_SSP->SR & (SSPSR_BSY|SSPSR_RNE)) != SSPSR_RNE );
+#endif
+#else
+ while ( !(LPC_SSP->SR & SSPSR_RNE) );
+#endif
+ *buf = LPC_SSP->DR;
+ buf++;
+
+ }
+ return;
+}
+
+/******************************************************************************
+** End Of File
+******************************************************************************/
+
diff --git a/software/mpu/src/ssp/ssp.h b/software/mpu/src/ssp/ssp.h new file mode 100644 index 0000000..4491687 --- /dev/null +++ b/software/mpu/src/ssp/ssp.h @@ -0,0 +1,109 @@ +/*****************************************************************************
+ * ssp.h: Header file for NXP LPC134x Family Microprocessors
+ *
+ * Copyright(C) 2006, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2006.07.19 ver 1.00 Preliminary version, first Release
+ *
+******************************************************************************/
+#ifndef __SSP_H__
+#define __SSP_H__
+
+/* There are there modes in SSP: loopback, master or slave. */
+/* Here are the combination of all the tests.
+(1) LOOPBACK test: LOOPBACK_MODE=1, TX_RX_ONLY=0, USE_CS=1;
+(2) Serial EEPROM test: LOOPBACK_MODE=0, TX_RX_ONLY=0, USE_CS=0; (default)
+(3) TX(Master) Only: LOOPBACK_MODE=0, SSP_SLAVE=0, TX_RX_ONLY=1, USE_CS=1;
+(4) RX(Slave) Only: LOOPBACK_MODE=0, SSP_SLAVE=1, TX_RX_ONLY=0, USE_CS=1 */
+
+#define LOOPBACK_MODE 0 /* 1 is loopback, 0 is normal operation. */
+#define SSP_SLAVE 0 /* 1 is SLAVE mode, 0 is master mode */
+#define TX_RX_ONLY 0 /* 1 is TX or RX only depending on SSP_SLAVE
+ flag, 0 is either loopback mode or communicate
+ with a serial EEPROM. */
+
+/* if USE_CS is zero, set SSEL as GPIO that you have total control of the sequence */
+/* When test serial SEEPROM(LOOPBACK_MODE=0, TX_RX_ONLY=0), set USE_CS to 0. */
+/* When LOOPBACK_MODE=1 or TX_RX_ONLY=1, set USE_CS to 1. */
+
+#define USE_CS 0
+#define SSP_DEBUG 0
+
+/* SPI read and write buffer size */
+#define SSP_BUFSIZE 16
+#define FIFOSIZE 8
+
+#define DELAY_COUNT 10
+#define MAX_TIMEOUT 0xFF
+
+/* Port0.2 is the SSP select pin */
+#define SSP0_SEL (1 << 2)
+
+/* SSP Status register */
+#define SSPSR_TFE (1 << 0)
+#define SSPSR_TNF (1 << 1)
+#define SSPSR_RNE (1 << 2)
+#define SSPSR_RFF (1 << 3)
+#define SSPSR_BSY (1 << 4)
+
+/* SSP CR0 register */
+#define SSPCR0_DSS (1 << 0)
+#define SSPCR0_FRF (1 << 4)
+#define SSPCR0_SPO (1 << 6)
+#define SSPCR0_SPH (1 << 7)
+#define SSPCR0_SCR (1 << 8)
+
+/* SSP CR1 register */
+#define SSPCR1_LBM (1 << 0)
+#define SSPCR1_SSE (1 << 1)
+#define SSPCR1_MS (1 << 2)
+#define SSPCR1_SOD (1 << 3)
+
+/* SSP Interrupt Mask Set/Clear register */
+#define SSPIMSC_RORIM (1 << 0)
+#define SSPIMSC_RTIM (1 << 1)
+#define SSPIMSC_RXIM (1 << 2)
+#define SSPIMSC_TXIM (1 << 3)
+
+/* SSP0 Interrupt Status register */
+#define SSPRIS_RORRIS (1 << 0)
+#define SSPRIS_RTRIS (1 << 1)
+#define SSPRIS_RXRIS (1 << 2)
+#define SSPRIS_TXRIS (1 << 3)
+
+/* SSP0 Masked Interrupt register */
+#define SSPMIS_RORMIS (1 << 0)
+#define SSPMIS_RTMIS (1 << 1)
+#define SSPMIS_RXMIS (1 << 2)
+#define SSPMIS_TXMIS (1 << 3)
+
+/* SSP0 Interrupt clear register */
+#define SSPICR_RORIC (1 << 0)
+#define SSPICR_RTIC (1 << 1)
+
+/* ATMEL SEEPROM command set */
+#define WREN 0x06 /* MSB A8 is set to 0, simplifying test */
+#define WRDI 0x04
+#define RDSR 0x05
+#define WRSR 0x01
+#define READ 0x03
+#define WRITE 0x02
+
+/* RDSR status bit definition */
+#define RDSR_RDY 0x01
+#define RDSR_WEN 0x02
+
+/* If RX_INTERRUPT is enabled, the SSP RX will be handled in the ISR
+SSPReceive() will not be needed. */
+extern void SSP_IRQHandler (void);
+extern void SSPInit( void );
+extern void SSPSend( uint8_t *Buf, uint32_t Length );
+extern void SSPReceive( uint8_t *buf, uint32_t Length );
+
+#endif /* __SSP_H__ */
+/*****************************************************************************
+** End Of File
+******************************************************************************/
+
diff --git a/software/mpu/src/ssp/ssptest.c b/software/mpu/src/ssp/ssptest.c new file mode 100644 index 0000000..119f8a7 --- /dev/null +++ b/software/mpu/src/ssp/ssptest.c @@ -0,0 +1,190 @@ +/*****************************************************************************
+ * ssptest.c: main C entry file for NXP LPC13xx Family Microprocessors
+ *
+ * Copyright(C) 2008, NXP Semiconductor
+ * All rights reserved.
+ *
+ * History
+ * 2008.07.19 ver 1.00 Preliminary version, first Release
+ *
+******************************************************************************/
+#include "LPC13xx.h" /* LPC13xx definitions */
+#include "../gpio/gpio.h"
+#include "ssp.h"
+#if SSP_DEBUG
+#include "uart.h"
+#endif
+
+/*****************************************************************************
+** Function name: LoopbackTest
+**
+** Descriptions: Loopback test
+**
+** parameters: None
+** Returned value: None
+**
+*****************************************************************************/
+void LoopbackTest( uint8_t* src_addr, uint8_t* dest_addr )
+{
+ uint32_t i;
+
+#if !USE_CS
+ /* Set SSEL pin to output low. */
+ GPIOSetValue( PORT0, 2, 0 );
+#endif
+ i = 0;
+ while ( i <= SSP_BUFSIZE )
+ {
+ /* to check the RXIM and TXIM interrupt, I send a block data at one time
+ based on the FIFOSIZE(8). */
+ SSPSend( (uint8_t *)&src_addr[i], FIFOSIZE );
+ /* If RX interrupt is enabled, below receive routine can be
+ also handled inside the ISR. */
+ SSPReceive( (uint8_t *)&dest_addr[i], FIFOSIZE );
+ i += FIFOSIZE;
+ }
+#if !USE_CS
+ /* Set SSEL pin to output high. */
+ GPIOSetValue( PORT0, 2, 1 );
+#endif
+
+ /* verifying write and read data buffer. */
+ for ( i = 0; i < SSP_BUFSIZE; i++ )
+ {
+ if ( src_addr[i] != dest_addr[i] )
+ {
+ while( 1 ); /* Verification failed */
+ }
+ }
+ return;
+}
+
+/*****************************************************************************
+** Function name: SEEPROMTest
+**
+** Descriptions: Serial EEPROM(Atmel 25xxx) test
+**
+** parameters: None
+** Returned value: None
+**
+*****************************************************************************/
+void SEEPROMTest( uint8_t* src_addr, uint8_t* dest_addr )
+{
+ uint32_t i, timeout;
+#if SSP_DEBUG
+ uint8_t temp[2];
+#endif
+
+ LPC_IOCON->PIO0_2 &= ~0x07; /* SSP SSEL is a GPIO pin */
+ GPIOSetValue( PORT0, 2, 1 );
+ /* port0, bit 2 is set to GPIO output and high */
+ GPIOSetDir( PORT0, 2, 1 );
+
+ GPIOSetValue( PORT0, 2, 0 );
+ /* Test Atmel 25016 SPI SEEPROM. */
+ src_addr[0] = WREN; /* set write enable latch */
+ SSPSend( (uint8_t *)src_addr, 1 );
+ GPIOSetValue( PORT0, 2, 1 );
+
+ for ( i = 0; i < DELAY_COUNT; i++ ); /* delay minimum 250ns */
+
+ GPIOSetValue( PORT0, 2, 0 );
+ src_addr[0] = RDSR; /* check status to see if write enabled is latched */
+ SSPSend( (uint8_t *)src_addr, 1 );
+ SSPReceive( (uint8_t *)dest_addr, 1 );
+ GPIOSetValue( PORT0, 2, 1 );
+ if ( (dest_addr[0] & (RDSR_WEN|RDSR_RDY)) != RDSR_WEN )
+ /* bit 0 to 0 is ready, bit 1 to 1 is write enable */
+ {
+ while ( 1 );
+ }
+
+ for ( i = 0; i < SSP_BUFSIZE; i++ ) /* Init RD and WR buffer */
+ {
+ src_addr[i+3] = i; /* leave three bytes for cmd and offset(16 bits) */
+ dest_addr[i] = 0;
+ }
+
+ /* please note the first two bytes of WR and RD buffer is used for
+ commands and offset, so only 2 through SSP_BUFSIZE is used for data read,
+ write, and comparison. */
+ GPIOSetValue( PORT0, 2, 0 );
+ src_addr[0] = WRITE; /* Write command is 0x02, low 256 bytes only */
+ src_addr[1] = 0x00; /* write address offset MSB is 0x00 */
+ src_addr[2] = 0x00; /* write address offset LSB is 0x00 */
+ SSPSend( (uint8_t *)src_addr, SSP_BUFSIZE );
+ GPIOSetValue( PORT0, 2, 1 );
+
+ for ( i = 0; i < 0x30000; i++ ); /* delay, minimum 3ms */
+
+ timeout = 0;
+ while ( timeout < MAX_TIMEOUT )
+ {
+ GPIOSetValue( PORT0, 2, 0 );
+ src_addr[0] = RDSR; /* check status to see if write cycle is done or not */
+ SSPSend( (uint8_t *)src_addr, 1);
+ SSPReceive( (uint8_t *)dest_addr, 1 );
+ GPIOSetValue( PORT0, 2, 1 );
+ if ( (dest_addr[0] & RDSR_RDY) == 0x00 ) /* bit 0 to 0 is ready */
+ {
+ break;
+ }
+ timeout++;
+ }
+ if ( timeout == MAX_TIMEOUT )
+ {
+ while ( 1 );
+ }
+
+ for ( i = 0; i < DELAY_COUNT; i++ ); /* delay, minimum 250ns */
+
+ GPIOSetValue( PORT0, 2, 0 );
+ src_addr[0] = READ; /* Read command is 0x03, low 256 bytes only */
+ src_addr[1] = 0x00; /* Read address offset MSB is 0x00 */
+ src_addr[2] = 0x00; /* Read address offset LSB is 0x00 */
+ SSPSend( (uint8_t *)src_addr, 3 );
+ SSPReceive( (uint8_t *)&dest_addr[3], SSP_BUFSIZE-3 );
+ GPIOSetValue( PORT0, 2, 1 );
+
+ /* verifying, ignore the difference in the first two bytes */
+ for ( i = 3; i < SSP_BUFSIZE; i++ )
+ {
+ if ( src_addr[i] != dest_addr[i] )
+ {
+#if SSP_DEBUG
+ temp[0] = (dest_addr[i] & 0xF0) >> 4;
+ if ( (temp[0] >= 0) && (temp[0] <= 9) )
+ {
+ temp[0] += 0x30;
+ }
+ else
+ {
+ temp[0] -= 0x0A;
+ temp[0] += 0x41;
+ }
+ temp[1] = dest_addr[i] & 0x0F;
+ if ( (temp[1] >= 0) && (temp[1] <= 9) )
+ {
+ temp[1] += 0x30;
+ }
+ else
+ {
+ temp[1] -= 0x0A;
+ temp[1] += 0x41;
+ }
+ UARTSend((uint8_t *)&temp[0], 2);
+ UARTSend("\r\n", 2);
+#endif
+ while( 1 ); /* Verification failed */
+ }
+ }
+#if SSP_DEBUG
+ UARTSend("PASS\r\n", 6);
+#endif
+ return;
+}
+
+/******************************************************************************
+** End Of File
+******************************************************************************/
+
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