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Diffstat (limited to 'software/hhd70dongle/c1101lib.c')
-rw-r--r--software/hhd70dongle/c1101lib.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/software/hhd70dongle/c1101lib.c b/software/hhd70dongle/c1101lib.c
index 2f0400e..ddbd28c 100644
--- a/software/hhd70dongle/c1101lib.c
+++ b/software/hhd70dongle/c1101lib.c
@@ -354,7 +354,7 @@ void c1101_init_ook_beacon(void)
// Data format = Synchronous serial mode
// Data rate = 1.00112
// RX filter BW = 58.035714
- // PA ramping = true
+ // PA ramping = false
// Preamble count = 2
// Address config = No address check
// Whitening = false
@@ -368,7 +368,7 @@ void c1101_init_ook_beacon(void)
// Base frequency = 435.199677
// Channel number = 0
// PA table
- char const pa_table[8] = {0x00,0x12,0x0e,0x34,0x60,0xc5,0xc1,0xc0};
+ char const pa_table[8] = {0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00};
//reset C1101
c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
@@ -384,10 +384,13 @@ void c1101_init_ook_beacon(void)
//enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO)
c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
// pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx)
+
//c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 0); //assert at 4 bytes in RX Fifo and 61 in TX Fifo
+
//c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0,0x12);//Packet Automation Control
c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+
c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1,0x06); //Frequency Synthesizer Control
c1101_spi_write_register(SPIC1101_ADDR_FREQ2,0x10); //Frequency Control Word, High Byte
c1101_spi_write_register(SPIC1101_ADDR_FREQ1,0xBD); //Frequency Control Word, Middle Byte
@@ -400,7 +403,7 @@ void c1101_init_ook_beacon(void)
c1101_spi_write_register(SPIC1101_ADDR_MCSM0,0x18); //Main Radio Control State Machine Configuration
c1101_spi_write_register(SPIC1101_ADDR_FOCCFG,0x16); //Frequency Offset Compensation Configuration
c1101_spi_write_register(SPIC1101_ADDR_WORCTRL,0xFB); //Wake On Radio Control
- c1101_spi_write_register(SPIC1101_ADDR_FREND0,0x17); //Front End TX Configuration
+ c1101_spi_write_register(SPIC1101_ADDR_FREND0,0x11); //Front End TX Configuration
c1101_spi_write_register(SPIC1101_ADDR_FSCAL3,0xE9); //Frequency Synthesizer Calibration
c1101_spi_write_register(SPIC1101_ADDR_FSCAL2,0x2A); //Frequency Synthesizer Calibration
c1101_spi_write_register(SPIC1101_ADDR_FSCAL1,0x00); //Frequency Synthesizer Calibration