Beacon Test (still RX Buffer underflow)

git-svn-id: https://svn.spreadspace.org/mur.sat@645 7de4ea59-55d0-425e-a1af-a3118ea81d4c

1 files changed, 100 insertions, 36 deletions

diff --git a/software/hhd70dongle/c1101lib.c b/software/hhd70dongle/c1101lib.c
index 6d4d876..a6dd5f4 100644
--- a/software/hhd70dongle/c1101lib.c
+++ b/software/hhd70dongle/c1101lib.c
@@ -258,6 +258,7 @@ void c1101_init(void)
     // PKTCTRL0      Packet Automation Control
     //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode
     c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+    //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000101); //crc enabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
     c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet
     // FSCTRL1       Frequency Synthesizer Control
     c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, 0x06);
@@ -303,31 +304,31 @@ void c1101_init(void)
 //Note for comparision:
 void c1101_init_w_rfstudiosettings1(void)
 {
-//  Sync word qualifier mode = 30/32 sync word bits detected
-//  CRC autoflush = false
-//  Channel spacing = 199.951172
-//  Data format = Normal mode
-//  Data rate = 9.59587
-//  RX filter BW = 58.035714
-//  PA ramping = true
-//  Preamble count = 4
-//  Address config = No address check
-//  Whitening = false
-//  Carrier frequency = 435.124695
-//  Device address = 0
-//  TX power = 10
-//  Manchester enable = false
-//  CRC enable = true
-//  Deviation = 11.901855
-//  Modulation format = GFSK
-//  Base frequency = 435.124695
-//  Modulated = true
-//  Channel number = 0
-//  PA table
+    //  Sync word qualifier mode = 30/32 sync word bits detected
+    //  CRC autoflush = false
+    //  Channel spacing = 199.951172
+    //  Data format = Normal mode
+    //  Data rate = 9.59587
+    //  RX filter BW = 58.035714
+    //  PA ramping = true
+    //  Preamble count = 4
+    //  Address config = No address check
+    //  Whitening = false
+    //  Carrier frequency = 435.124695
+    //  Device address = 0
+    //  TX power = 10
+    //  Manchester enable = false
+    //  CRC enable = true
+    //  Deviation = 11.901855
+    //  Modulation format = GFSK
+    //  Base frequency = 435.124695
+    //  Modulated = true
+    //  Channel number = 0
+    //  PA table
     char const pa_table[8] = {0x00,0x12,0x0e,0x34,0x60,0xc5,0xc1,0xc0};
-//
-// Rf settings for CC1101
-//
+    //
+    // Rf settings for CC1101
+    //
     //reset C1101
     c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
     _delay_ms(100);
@@ -344,6 +345,66 @@ void c1101_init_w_rfstudiosettings1(void)
 }
 
 
+void c1101_init_ook_beacon(void)
+{
+    //  Sync word qualifier mode = No preamble/sync
+    //  CRC autoflush = false
+    //  Channel spacing = 49.987793
+    //  Data format = Synchronous serial mode
+    //  Data rate = 1.00112
+    //  RX filter BW = 58.035714
+    //  PA ramping = true
+    //  Preamble count = 2
+    //  Address config = No address check
+    //  Whitening = false
+    //  Carrier frequency = 435.199677
+    //  Device address = 0
+    //  TX power = 10
+    //  Manchester enable = false
+    //  CRC enable = false
+    //  Deviation = 2.975464
+    //  Modulation format = ASK/OOK
+    //  Base frequency = 435.199677
+    //  Channel number = 0
+    //  PA table
+    char const pa_table[8] = {0x00,0x12,0x0e,0x34,0x60,0xc5,0xc1,0xc0};
+
+    //reset C1101
+    c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
+    _delay_ms(100);
+    //flush FIFOs
+    c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
+    c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
+
+    //
+    // Rf settings for CC1101
+    //
+    c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x80);
+    //enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO)
+    c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
+    // pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx)
+    c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
+    c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0,0x12);//Packet Automation Control
+    c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1,0x06); //Frequency Synthesizer Control
+    c1101_spi_write_register(SPIC1101_ADDR_FREQ2,0x10);   //Frequency Control Word, High Byte
+    c1101_spi_write_register(SPIC1101_ADDR_FREQ1,0xBD);   //Frequency Control Word, Middle Byte
+    c1101_spi_write_register(SPIC1101_ADDR_FREQ0,0x0B);   //Frequency Control Word, Low Byte
+    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4,0xF5); //Modem Configuration
+    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3,0x43); //Modem Configuration
+    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2,0x30); //Modem Configuration
+    c1101_spi_write_register(SPIC1101_ADDR_MDMCFG1,0x00); //Modem Configuration
+    c1101_spi_write_register(SPIC1101_ADDR_DEVIATN,0x07); //Modem Deviation Setting
+    c1101_spi_write_register(SPIC1101_ADDR_MCSM0,0x18);   //Main Radio Control State Machine Configuration
+    c1101_spi_write_register(SPIC1101_ADDR_FOCCFG,0x16);  //Frequency Offset Compensation Configuration
+    c1101_spi_write_register(SPIC1101_ADDR_WORCTRL,0xFB); //Wake On Radio Control
+    c1101_spi_write_register(SPIC1101_ADDR_FREND0,0x17);  //Front End TX Configuration
+    c1101_spi_write_register(SPIC1101_ADDR_FSCAL3,0xE9);  //Frequency Synthesizer Calibration
+    c1101_spi_write_register(SPIC1101_ADDR_FSCAL2,0x2A);  //Frequency Synthesizer Calibration
+    c1101_spi_write_register(SPIC1101_ADDR_FSCAL1,0x00);  //Frequency Synthesizer Calibration
+    c1101_spi_write_register(SPIC1101_ADDR_FSCAL0,0x1F);  //Frequency Synthesizer Calibration
+    c1101_spi_write_patable(pa_table);
+}
+
 //f_XOSC = 26Mhz
 // freq:            desired_carrier_freq [Hz] *2^16 / f_XOSC
 // freq_offset:     desired frequency offset [Hz] *2^14 / f_XOSC
@@ -475,7 +536,7 @@ void c1101_transmitData(char *buffer, unsigned int len)
     //~ (debug_sb,255);
 
     //enable Power Amplifier
-    hhd70_palna_txmode();
+    hhd70_palna_txmode();  //should actually be done by c1101 itself, by connecting PTT function of GPO0 pin to LNA/PA toggle
 
     //keep buffer filled
     uint8_t c1101_state=0;
@@ -485,15 +546,17 @@ void c1101_transmitData(char *buffer, unsigned int len)
         num_written = c1101_spi_write_txfifo(buffer,  len );
         buffer += num_written;
         len -= num_written;
-        c1101_state = c1101_getMARCState();
-        if (c1101_state == 1 || (c1101_state >= 13  && c1101_state <= 15))
+
+        //wait until in IDLE or RX State:
+        do
         {
-            //from state IDLE or RX go to TX
-            num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX);
-            //~ ((uint8_t*)"Strobe STX",255);
-            //~ debug_sprint_int16hex(debug_sb, num_written);
-            //~ (debug_sb,255);
+            c1101_state = c1101_getMARCState();
+            _delay_ms(100);
         }
+        while (!(c1101_state == 1 || (c1101_state >= 13  && c1101_state <= 15)));
+        //from state IDLE or RX go to TX
+        num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX);
+
         //~ ((uint8_t*)"TX2 num written",255);
         //~ debug_sprint_int16hex(debug_sb, num_written);
         //~ (debug_sb,255);
@@ -505,15 +568,16 @@ void c1101_transmitData(char *buffer, unsigned int len)
         //~ (debug_sb,255);
     } while (len > 0);
 
-    //disable Power Amplifier
-    //FIXME, instead use PTT function of GPO0 -> interrupt handler -> toggle rx/tx
-    //wait until RX finished
+    //wait until TX finished
     do
     {
         c1101_state = c1101_getMARCState();
-        _delay_ms(1);
+        _delay_ms(100);
     }
     while (c1101_state == 19 || c1101_state == 20);
+
+    //disable Power Amplifier
+    //FIXME, instead use PTT function of GPO0 -> interrupt handler -> toggle rx/tx
     hhd70_palna_rxmode();
 }