hhd70dongle: fixes for frequency calcualtion, improved support for c1101 power settings

1 files changed, 65 insertions, 23 deletions

diff --git a/software/hhd70dongle/c1101lib.c b/software/hhd70dongle/c1101lib.c
index d7c78ee..c24c398 100644
--- a/software/hhd70dongle/c1101lib.c
+++ b/software/hhd70dongle/c1101lib.c
@@ -12,6 +12,7 @@
  *
  *
  *  Copyright (C) 2012 Bernhard Tittelbach <xro@realraum.at>
+ *                2015 Christian Pointner <equinox@mur.at>
  *
  *  This file is part of mur.sat.
  *
@@ -203,7 +204,7 @@ int c1101_spi_write_txfifo(char *buffer, int len)
 }
 
 //patable muste be char array of length 8
-int c1101_spi_write_patable(char const patable[])
+int c1101_spi_write_patable(uint8_t const patable[])
 {
     int16_t sb;
     int8_t len = 8;
@@ -222,6 +223,21 @@ int c1101_spi_write_patable(char const patable[])
 }
 
 
+static uint8_t const pa_table_values_[] = { 0x00, 0x30, 0x20, 0x10, 0x01, 0x02, 0x11, 0x03,
+                    0x12, 0x04, 0x05, 0x13, 0x06, 0x07, 0x21, 0x14, 0x08, 0x09, 0x0A, 0x15,
+                    0x0B, 0x31, 0x16, 0x0C, 0x0D, 0x0E, 0x17, 0x0F, 0x22, 0x18, 0x19, 0x1A,
+                    0x1B, 0x32, 0x23, 0x1C, 0x6F, 0x1D, 0x1E, 0x1F, 0x24, 0x33, 0x25, 0x34,
+                    0x26, 0x6E, 0x27, 0x35, 0x28, 0x6D, 0x6C, 0x29, 0x36, 0x6B, 0x2A, 0x6A,
+                    0x37, 0x69, 0x2B, 0x68, 0x38, 0x2C, 0x8F, 0x67, 0x2D, 0x57, 0x39, 0x66,
+                    0x2E, 0x56, 0x3A, 0x2F, 0x65, 0x55, 0x3B, 0x64, 0x54, 0x3C, 0x63, 0x3D,
+                    0x53, 0x3E, 0x62, 0x3F, 0x52, 0x40, 0x61, 0x51, 0x60, 0x50, 0x8E, 0x8D,
+                    0x8C, 0xCF, 0x8B, 0x8A, 0x89, 0x88, 0x87, 0x86, 0x85, 0xCE, 0x84, 0x83,
+                    0xCD, 0x82, 0xCC, 0x81, 0xCB, 0x80, 0xCA, 0xC9, 0xC8, 0xC7, 0xC6, 0xC5,
+                    0xC4, 0xC3, 0xC2, 0xC1, 0xC0 };
+
+#define PA_TABLE_VALUES_MAX ((sizeof(pa_table_values_)/sizeof(uint8_t))-1)
+static uint8_t ook_power_ = 83; // ==> 3F
+
 /**** External Functions ****/
 
 uint16_t c1101_setFSKDeviationFromCarrier(int8_t m, int8_t e)
@@ -292,7 +308,7 @@ void c1101_init(void)
 
     //AFU Satellite Band: 435.000 - 438.000 kHz
     //AFU Salellite Band Max Bandwith: 20 kHz
-    
+
     hhd70_config_GDO0_OOK_output(false);
 }
 
@@ -320,7 +336,7 @@ void c1101_init_w_rfstudiosettings1(void)
     //  Modulated = true
     //  Channel number = 0
     //  PA table
-    char const pa_table[8] = {0x00,0x12,0x0e,0x34,0x60,0xc5,0xc1,0xc0};
+    uint8_t const pa_table[8] = {0x00,0x12,0x0e,0x34,0x60,0xc5,0xc1,0xc0};
     //
     // Rf settings for CC1101
     //
@@ -337,7 +353,7 @@ void c1101_init_w_rfstudiosettings1(void)
 
     //Values from SmartRFStudio:
     c1101_spi_write_patable(pa_table);
-    
+
     hhd70_config_GDO0_OOK_output(false);
 }
 
@@ -354,21 +370,16 @@ void c1101_init_ook_beacon(void)
     //  Preamble count = 2
     //  Address config = No address check
     //  Whitening = false
-    //  Carrier frequency = 435.199677
+    //  Carrier frequency = 437.524902 MHz
     //  Device address = 0
     //  TX power = 10
     //  Manchester enable = false
     //  CRC enable = false
     //  Deviation = 2.975464
     //  Modulation format = ASK/OOK
-    //  Base frequency = 435.199677
+    //  Base frequency = 437.524902 MHz
     //  Channel number = 0
     //  PA table by TI
-    //char const pa_table[8] = {0x00,0x12,0x0e,0x34,0x60,0xc5,0xc1,0xc0};
-    // not recommended for OOK even with PA ramping set to false
-    //char const pa_table[8] = {0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00};
-    // correct PA table for OOK (only first two values matter)
-    char const pa_table[8] = {0x00,0xc5,0xc5,0xc5,0xc5,0xc5,0xc5,0xc5};
 
     //reset C1101
     c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
@@ -388,11 +399,11 @@ void c1101_init_ook_beacon(void)
     c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 0);  //assert at 4 bytes in RX Fifo and 61 in TX Fifo
     //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0,0x12);//Packet Automation Control
     //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
-    c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000110001); //crc disabled; asynchronous serial input on GDO0 
+    c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000110001); //crc disabled; asynchronous serial input on GDO0
     c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1,0x06); //Frequency Synthesizer Control
     c1101_spi_write_register(SPIC1101_ADDR_FREQ2,0x10);   //Frequency Control Word, High Byte
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ1,0xBD);   //Frequency Control Word, Middle Byte
-    c1101_spi_write_register(SPIC1101_ADDR_FREQ0,0x0B);   //Frequency Control Word, Low Byte
+    c1101_spi_write_register(SPIC1101_ADDR_FREQ1,0xD3);   //Frequency Control Word, Middle Byte
+    c1101_spi_write_register(SPIC1101_ADDR_FREQ0,0xF0);   //Frequency Control Word, Low Byte
     c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4,0xF5); //Modem Configuration
     c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3,0x43); //Modem Configuration
     c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2,0x30); //Modem Configuration
@@ -406,11 +417,42 @@ void c1101_init_ook_beacon(void)
     c1101_spi_write_register(SPIC1101_ADDR_FSCAL2,0x2A);  //Frequency Synthesizer Calibration
     c1101_spi_write_register(SPIC1101_ADDR_FSCAL1,0x00);  //Frequency Synthesizer Calibration
     c1101_spi_write_register(SPIC1101_ADDR_FSCAL0,0x1F);  //Frequency Synthesizer Calibration
-    c1101_spi_write_patable(pa_table);
-    
+
+    c1101_ook_power_set(ook_power_);
     hhd70_config_GDO0_OOK_output(true);
 }
 
+uint8_t c1101_ook_power_get()
+{
+    return ook_power_;
+}
+
+uint8_t c1101_ook_power_get_raw()
+{
+    return pa_table_values_[ook_power_];
+}
+
+void c1101_ook_power_set(uint8_t power)
+{
+    uint8_t val = pa_table_values_[(power <= PA_TABLE_VALUES_MAX) ? power : PA_TABLE_VALUES_MAX];
+    uint8_t const pa_table[8] = {0x00, val ,0x00,0x00,0x00,0x00,0x00,0x00};
+    c1101_spi_write_patable(pa_table);
+}
+
+void c1101_ook_power_inc()
+{
+    ook_power_ = (ook_power_ < PA_TABLE_VALUES_MAX) ? ook_power_ + 1 : PA_TABLE_VALUES_MAX;
+    uint8_t const pa_table[8] = {0x00, pa_table_values_[ook_power_] ,0x00,0x00,0x00,0x00,0x00,0x00};
+    c1101_spi_write_patable(pa_table);
+}
+
+void c1101_ook_power_dec()
+{
+    ook_power_ = (ook_power_ > 0) ? ook_power_ - 1 : 0;
+    uint8_t const pa_table[8] = {0x00, pa_table_values_[ook_power_] ,0x00,0x00,0x00,0x00,0x00,0x00};
+    c1101_spi_write_patable(pa_table);
+}
+
 // see Datasheet Chapter 14.1 Frequency Offset Compensation
 // freq_offset:     desired frequency offset [Hz] *2^14 / f_XTAL
 //f_XTAL = 26Mhz
@@ -554,7 +596,7 @@ bool c1101_writeFrequencyRegisters(uint32_t freq)
 {
     if (! c1101_waitUntilIDLEState(2000)) //wait 2sec max
         return false;
-    //programm frequency    
+    //programm frequency
     c1101_spi_write_register(SPIC1101_ADDR_FREQ0, freq & 0xFF);
     c1101_spi_write_register(SPIC1101_ADDR_FREQ1, (freq >> 8) & 0xFF);
     c1101_spi_write_register(SPIC1101_ADDR_FREQ2, (freq >> 16) & 0x3F);
@@ -570,7 +612,7 @@ uint32_t c1101_readFrequencyRegisters(void)
     freq = ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ2)) & 0x3F;
     freq = freq << 8;
     freq |= ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ1));
-    freq = freq << 8;   
+    freq = freq << 8;
     freq |= ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ0));
     return freq;
 }
@@ -579,7 +621,7 @@ uint32_t c1101_readFrequencyRegisters(void)
 // freq:            desired_carrier_freq [Hz] *2^16 / f_XOSC
 bool c1101_setFrequency(uint32_t freq_hz)
 {
-    uint32_t freq = freq_hz / 397;
+    uint32_t freq = (uint32_t)((float)freq_hz / C1101_FREQ_TO_HZ);
     if ( freq <= 0x3FFFFF)
         return c1101_writeFrequencyRegisters(freq);
     else
@@ -590,11 +632,11 @@ bool c1101_setFrequency(uint32_t freq_hz)
 // freq:            desired_carrier_freq [Hz] *2^16 / f_XOSC
 bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz)
 {
-    int32_t freq_change = freq_change_hz / 397;
+    int32_t freq_change = (int32_t)((float)freq_change_hz / C1101_FREQ_TO_HZ);
     int32_t freq = (int32_t) c1101_readFrequencyRegisters();
-       
+
     freq += freq_change;
-    
+
     if ( freq >= 0 && freq <= 0x3FFFFF )
         return c1101_writeFrequencyRegisters((uint32_t) freq);
     else
@@ -603,7 +645,7 @@ bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz)
 
 uint32_t c1101_getCurrentCarrierFrequencyHz(void)
 {
-    return c1101_readFrequencyRegisters() * 397;
+  return (uint32_t)((float)c1101_readFrequencyRegisters() * C1101_FREQ_TO_HZ);
 }
 
 // if_freq:         desired intermidiate rx frequency [Hz] *2^10 / f_XOSC