diff options
author | Christian Pointner <equinox@mur.at> | 2013-02-27 14:42:10 +0000 |
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committer | Christian Pointner <equinox@mur.at> | 2013-02-27 14:42:10 +0000 |
commit | 4cd9b12c1868611d9f129983145ba276b09160f3 (patch) | |
tree | 74efc58c72728e578a053381e3a74af2e53e2248 /software/avr.lib/util.c | |
parent | rda1846dongle: finished gnd vias (diff) |
merged fixes and new Boards from avr utils
git-svn-id: https://svn.spreadspace.org/mur.sat@681 7de4ea59-55d0-425e-a1af-a3118ea81d4c
Diffstat (limited to 'software/avr.lib/util.c')
-rw-r--r-- | software/avr.lib/util.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/software/avr.lib/util.c b/software/avr.lib/util.c index 3de042e..3aa1a37 100644 --- a/software/avr.lib/util.c +++ b/software/avr.lib/util.c @@ -49,7 +49,7 @@ void cpu_init(void) #define BOOTLOADER_VEC 0x3000 #elif defined(__BOARD_minimus32__) #define BOOTLOADER_VEC 0x3800 -#elif defined(__BOARD_hhd70dongle__) || defined(__BOARD_culV3__) +#elif defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) #define BOOTLOADER_VEC 0x3800 #else #define BOOTLOADER_VEC 0x0000 @@ -61,7 +61,8 @@ f_ptr_type start_bootloader = (f_ptr_type)BOOTLOADER_VEC; void reset2bootloader(void) { #if defined(__BOARD_teensy1__) || defined(__BOARD_teensy1pp__) || defined(__BOARD_teensy2__) || defined(__BOARD_teensy2pp__) || \ - defined(__BOARD_hhd70dongle__) || defined(__BOARD_culV3__) || defined(__BOARD_minimus__) || defined(__BOARD_minimus32__) + defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) || \ + defined(__BOARD_minimus__) || defined(__BOARD_minimus32__) cli(); // disable watchdog, if enabled // disable all peripherals @@ -99,7 +100,7 @@ void reset2bootloader(void) TIMSK0 = 0; TIMSK1 = 0; UCSR1B = 0; DDRB = 0; DDRC = 0; DDRD = 0; PORTB = 0; PORTC = 0; PORTD = 0; - #elif defined(__BOARD_hhd70dongle__) || defined(__culV3__) + #elif defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0; TIMSK0 = 0; TIMSK1 = 0; TIMSK3 = 0; TIMSK4 = 0; UCSR1B = 0; TWCR = 0; DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0; TWCR = 0; |