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authorChristian Pointner <equinox@mur.at>2013-06-14 12:50:55 +0000
committerChristian Pointner <equinox@mur.at>2013-06-14 12:50:55 +0000
commit82ea3e4ecf54deb65026230562d546d15ecb6ca3 (patch)
treef8eca4ff5e5fad131cf52662a0bab282d7b6d066 /contrib
parentsome routing done - dead end?? (diff)
some cleanup
added SDIO pinout git-svn-id: https://svn.spreadspace.org/mur.sat@783 7de4ea59-55d0-425e-a1af-a3118ea81d4c
Diffstat (limited to 'contrib')
-rw-r--r--contrib/kicad-libs/mur-sat.lib22
1 files changed, 11 insertions, 11 deletions
diff --git a/contrib/kicad-libs/mur-sat.lib b/contrib/kicad-libs/mur-sat.lib
index 0ffa097..a59ba45 100644
--- a/contrib/kicad-libs/mur-sat.lib
+++ b/contrib/kicad-libs/mur-sat.lib
@@ -1,4 +1,4 @@
-EESchema-LIBRARY Version 2.3 Date: Di 11 Jun 2013 02:04:33 CEST
+EESchema-LIBRARY Version 2.3 Date: Fre 14 Jun 2013 14:49:32 CEST
#encoding utf-8
#
# AD8027
@@ -1089,32 +1089,32 @@ X PC1/ADC12_IN11 9 -1400 1550 200 R 50 50 1 1 B
X PC2/ADC12_IN12 10 -1400 1450 200 R 50 50 1 1 B
X PA4/SPI1_NSS 20 1450 1250 200 L 50 50 1 1 B
X PB11/I2C2_SDA 30 1450 -1300 200 L 50 50 1 1 B
-X PC9 40 -1400 750 200 R 50 50 1 1 B
+X PC9/SDIO_D1 40 -1400 750 200 R 50 50 1 1 B
X PA15 50 1450 150 200 L 50 50 1 1 B
X BOOT0 60 -1400 -1450 200 R 50 50 1 1 I
X PC3/ADC12_IN13 11 -1400 1350 200 R 50 50 1 1 B
X PA5/SPI1_SCK 21 1450 1150 200 L 50 50 1 1 B
X Vss_1 31 -100 -2050 200 U 50 50 1 1 W
X PA8/UASRT1_CK 41 1450 850 200 L 50 50 1 1 B
-X PC10 51 -1400 650 200 R 50 50 1 1 B
-X PB8/TIM4_CH3 61 1450 -1000 200 L 50 50 1 1 B
+X PC10/SDIO_D2 51 -1400 650 200 R 50 50 1 1 B
+X PB8/TIM4_CH3/SDIO_D4 61 1450 -1000 200 L 50 50 1 1 B
X Vss_A 12 -250 -2050 200 U 50 50 1 1 W
X PA6/SPI1_MISO 22 1450 1050 200 L 50 50 1 1 B
X Vdd_1 32 -100 2000 200 D 50 50 1 1 W
X PA9/UASRT1_TX 42 1450 750 200 L 50 50 1 1 B
-X PC11 52 -1400 550 200 R 50 50 1 1 B
-X PB9/TIM4_CH4 62 1450 -1100 200 L 50 50 1 1 B
+X PC11/SDIO_D3 52 -1400 550 200 R 50 50 1 1 B
+X PB9/TIM4_CH4/SDIO_D5 62 1450 -1100 200 L 50 50 1 1 B
X Vdd_A 13 -350 2000 200 D 50 50 1 1 W
X PA7/SPI1_MOSI 23 1450 950 200 L 50 50 1 1 B
X PB12/SPI2_NSS 33 1450 -1400 200 L 50 50 1 1 B
X PA10/UASRT1_RX 43 1450 650 200 L 50 50 1 1 B
-X PC12 53 -1400 450 200 R 50 50 1 1 B
+X PC12/SDIO_CK 53 -1400 450 200 R 50 50 1 1 B
X Vss_3 63 100 -2050 200 U 50 50 1 1 W
X PA0/WKUP/USART2_CTS 14 1450 1650 200 L 50 50 1 1 B
X PC4/ADC12_IN14 24 -1400 1250 200 R 50 50 1 1 B
X PB13/SPI2_SCK 34 1450 -1500 200 L 50 50 1 1 B
X PA11/USART1_CTS 44 1450 550 200 L 50 50 1 1 B
-X PD2/TIM3_ETR 54 -1400 -1200 200 R 50 50 1 1 B
+X PD2/TIM3_ETR/SDIO_CMD 54 -1400 -1200 200 R 50 50 1 1 B
X Vdd_3 64 100 2000 200 D 50 50 1 1 W
X PA1/USART2_RTS 15 1450 1550 200 L 50 50 1 1 B
X PC5/ADC12_IN15 25 -1400 1150 200 R 50 50 1 1 B
@@ -1128,17 +1128,17 @@ X PA13 46 1450 350 200 L 50 50 1 1 B
X PB4/JNTRST 56 1450 -600 200 L 50 50 1 1 B
X PA3/USART2_RX 17 1450 1350 200 L 50 50 1 1 B
X PB1/ADC12_IN9 27 1450 -300 200 L 50 50 1 1 B
-X PC6 37 -1400 1050 200 R 50 50 1 1 B
+X PC6/SDIO_D6 37 -1400 1050 200 R 50 50 1 1 B
X Vss_2 47 0 -2050 200 U 50 50 1 1 W
X PB5/I2C1_SMBAI 57 1450 -700 200 L 50 50 1 1 B
X Vss_4 18 200 -2050 200 U 50 50 1 1 W
X PB2/BOOT1 28 1450 -400 200 L 50 50 1 1 B
-X PC7 38 -1400 950 200 R 50 50 1 1 B
+X PC7/SDIO_D7 38 -1400 950 200 R 50 50 1 1 B
X Vdd_2 48 0 2000 200 D 50 50 1 1 W
X PB6/I2C1_SCL 58 1450 -800 200 L 50 50 1 1 B
X Vdd_4 19 200 2000 200 D 50 50 1 1 W
X PB10/I2C2_SCL 29 1450 -1200 200 L 50 50 1 1 B
-X PC8 39 -1400 850 200 R 50 50 1 1 B
+X PC8/SDIO_D0 39 -1400 850 200 R 50 50 1 1 B
X PA14 49 1450 250 200 L 50 50 1 1 B
X PB7/I2C1_SDA 59 1450 -900 200 L 50 50 1 1 B
ENDDRAW