diff options
Diffstat (limited to 'lib/util.c')
| -rw-r--r-- | lib/util.c | 9 |
1 files changed, 5 insertions, 4 deletions
@@ -51,7 +51,7 @@ void cpu_init(void) #define BOOTLOADER_VEC 0x3800 #elif defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) #define BOOTLOADER_VEC 0x3800 -#elif defined(__BOARD_slowpandongle__) +#elif defined(__BOARD_slowpandongle1__) || defined(__BOARD_slowpandongle2__) #define BOOTLOADER_VEC 0x3800 #else #define BOOTLOADER_VEC 0x0000 @@ -63,7 +63,8 @@ f_ptr_type start_bootloader = (f_ptr_type)BOOTLOADER_VEC; void reset2bootloader(void) { #if defined(__BOARD_teensy1__) || defined(__BOARD_teensy1pp__) || defined(__BOARD_teensy2__) || defined(__BOARD_teensy2pp__) || \ - defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) || defined(__BOARD_slowpandongle__) || \ + defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) || \ + defined(__BOARD_slowpandongle1__) || defined(__BOARD_slowpandongle2__) || \ defined(__BOARD_minimus__) || defined(__BOARD_minimus32__) cli(); // disable watchdog, if enabled @@ -92,7 +93,7 @@ void reset2bootloader(void) TIMSK0 = 0; TIMSK1 = 0; TIMSK2 = 0; TIMSK3 = 0; UCSR1B = 0; TWCR = 0; DDRA = 0; DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0; PORTA = 0; PORTB = 0; PORTC = 0; PORTD = 0; PORTE = 0; PORTF = 0; - #elif defined(__BOARD_minimus__) || defined(__BOARD_slowpandongle__) + #elif defined(__BOARD_minimus__) || defined(__BOARD_slowpandongle1__) EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; TIMSK0 = 0; TIMSK1 = 0; UCSR1B = 0; DDRB = 0; DDRC = 0; DDRD = 0; @@ -102,7 +103,7 @@ void reset2bootloader(void) TIMSK0 = 0; TIMSK1 = 0; UCSR1B = 0; DDRB = 0; DDRC = 0; DDRD = 0; PORTB = 0; PORTC = 0; PORTD = 0; - #elif defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) + #elif defined(__BOARD_hhd70dongle2__) || defined(__BOARD_hhd70dongle__) || defined(__BOARD_rda1846dongle__) || defined(__BOARD_culV3__) EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0; TIMSK0 = 0; TIMSK1 = 0; TIMSK3 = 0; TIMSK4 = 0; UCSR1B = 0; TWCR = 0; DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0; TWCR = 0; |