multi-byte register write access now uses burst mode as well

1 files changed, 61 insertions, 30 deletions

diff --git a/lib/cc1101.c b/lib/cc1101.c
index 0bf604b..99c732c 100644
--- a/lib/cc1101.c
+++ b/lib/cc1101.c
@@ -290,8 +290,6 @@ cc1101_state_t cc1101_get_state(void)
 
 
 
-
-
 uint32_t cc1101_get_freq_hz(void)
 {
   return (uint32_t)((float)(cc1101_get_freq()) * drv.freq_corr);
@@ -362,9 +360,12 @@ uint16_t cc1101_get_sync(void)
 
 void cc1101_set_sync(uint16_t sync)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_SYNC0, (uint8_t)(sync) & CC1101_REG_RW_SYNC0_MASK);
+  uint8_t data[2];
+  data[1] = (uint8_t)sync & CC1101_REG_RW_SYNC0_MASK;
   sync = sync >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_SYNC1, (uint8_t)(sync) & CC1101_REG_RW_SYNC1_MASK);
+  data[0] = (uint8_t)sync & CC1101_REG_RW_SYNC1_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_SYNC1, data, 2);
 }
 
 uint8_t cc1101_get_pktlen(void)
@@ -390,9 +391,12 @@ uint16_t cc1101_get_pktctrl(void)
 
 void cc1101_set_pktctrl(uint16_t ctrl)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, (uint8_t)(ctrl) & CC1101_REG_RW_PKTCTRL0_MASK);
+  uint8_t data[2];
+  data[1] = (uint8_t)ctrl & CC1101_REG_RW_PKTCTRL0_MASK;
   ctrl = ctrl >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_PKTCTRL1, (uint8_t)(ctrl) & CC1101_REG_RW_PKTCTRL1_MASK);
+  data[0] = (uint8_t)ctrl & CC1101_REG_RW_PKTCTRL1_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_PKTCTRL1, data, 2);
 }
 
 uint8_t cc1101_get_addr(void)
@@ -451,11 +455,14 @@ uint32_t cc1101_get_freq(void)
 
 void cc1101_set_freq(uint32_t freq)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_FREQ0, (uint8_t)(freq) & CC1101_REG_RW_FREQ0_MASK);
+  uint8_t data[3];
+  data[2] = (uint8_t)freq & CC1101_REG_RW_FREQ0_MASK;
   freq = freq >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_FREQ1, (uint8_t)(freq) & CC1101_REG_RW_FREQ1_MASK);
+  data[1] = (uint8_t)freq & CC1101_REG_RW_FREQ1_MASK;
   freq = freq >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_FREQ2, (uint8_t)(freq) & CC1101_REG_RW_FREQ2_MASK);
+  data[0] = (uint8_t)freq & CC1101_REG_RW_FREQ2_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_FREQ2, data, 3);
 }
 
 uint32_t cc1101_get_modemcfg(void)
@@ -473,11 +480,14 @@ uint32_t cc1101_get_modemcfg(void)
 
 void cc1101_set_modemcfg(uint32_t cfg)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_MDMCFG0, cfg & CC1101_REG_RW_MDMCFG0_MASK);
+  uint8_t data[3];
+  data[2] = (uint8_t)cfg & CC1101_REG_RW_MDMCFG0_MASK;
   cfg = cfg >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_MDMCFG1, cfg & CC1101_REG_RW_MDMCFG1_MASK);
+  data[1] = (uint8_t)cfg & CC1101_REG_RW_MDMCFG1_MASK;
   cfg = cfg >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_MDMCFG2, cfg & CC1101_REG_RW_MDMCFG2_MASK);
+  data[0] = (uint8_t)cfg & CC1101_REG_RW_MDMCFG2_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_MDMCFG2, data, 3);
 }
 
 uint16_t cc1101_get_drate_bw(void)
@@ -493,9 +503,12 @@ uint16_t cc1101_get_drate_bw(void)
 
 void cc1101_set_drate_bw(uint16_t cfg)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_MDMCFG3, cfg & CC1101_REG_RW_MDMCFG3_MASK);
+  uint8_t data[2];
+  data[1] = (uint8_t)cfg & CC1101_REG_RW_MDMCFG3_MASK;
   cfg = cfg >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_MDMCFG4, cfg & CC1101_REG_RW_MDMCFG4_MASK);
+  data[0] = (uint8_t)cfg & CC1101_REG_RW_MDMCFG4_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_MDMCFG4, data, 2);
 }
 
 uint8_t cc1101_get_deviatn(void)
@@ -525,11 +538,14 @@ uint32_t cc1101_get_mcsm(void)
 
 void cc1101_set_mcsm(uint32_t cfg)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_MCSM0, cfg & CC1101_REG_RW_MCSM0_MASK);
+  uint8_t data[3];
+  data[2] = (uint8_t)cfg & CC1101_REG_RW_MCSM0_MASK;
   cfg = cfg >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_MCSM1, cfg & CC1101_REG_RW_MCSM1_MASK);
+  data[1] = (uint8_t)cfg & CC1101_REG_RW_MCSM1_MASK;
   cfg = cfg >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_MCSM2, cfg & CC1101_REG_RW_MCSM2_MASK);
+  data[0] = (uint8_t)cfg & CC1101_REG_RW_MCSM2_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_MCSM2, data, 3);
 }
 
 
@@ -568,11 +584,14 @@ uint32_t cc1101_get_agcctrl(void)
 
 void cc1101_set_agcctrl(uint32_t ctrl)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_AGCCTRL0, ctrl & CC1101_REG_RW_AGCCTRL0_MASK);
+  uint8_t data[3];
+  data[2] = (uint8_t)ctrl & CC1101_REG_RW_AGCCTRL0_MASK;
   ctrl = ctrl >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_AGCCTRL1, ctrl & CC1101_REG_RW_AGCCTRL1_MASK);
+  data[1] = (uint8_t)ctrl & CC1101_REG_RW_AGCCTRL1_MASK;
   ctrl = ctrl >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_AGCCTRL2, ctrl & CC1101_REG_RW_AGCCTRL2_MASK);
+  data[0] = (uint8_t)ctrl & CC1101_REG_RW_AGCCTRL2_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_AGCCTRL2, data, 3);
 }
 
 uint16_t cc1101_get_worevt(void)
@@ -588,9 +607,12 @@ uint16_t cc1101_get_worevt(void)
 
 void cc1101_set_worevt(uint16_t timeout)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_WOREVT0, timeout & CC1101_REG_RW_WOREVT0_MASK);
+  uint8_t data[2];
+  data[1] = (uint8_t)timeout & CC1101_REG_RW_WOREVT0_MASK;
   timeout = timeout >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_WOREVT1, timeout & CC1101_REG_RW_WOREVT1_MASK);
+  data[0] = (uint8_t)timeout & CC1101_REG_RW_WOREVT1_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_WOREVT1, data, 2);
 }
 
 uint8_t cc1101_get_worctrl(void)
@@ -617,9 +639,12 @@ uint16_t cc1101_get_frend(void)
 
 void cc1101_set_frend(uint16_t cfg)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_FREND0, cfg & CC1101_REG_RW_FREND0_MASK);
+  uint8_t data[2];
+  data[1] = (uint8_t)cfg & CC1101_REG_RW_FREND0_MASK;
   cfg = cfg >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_FREND1, cfg & CC1101_REG_RW_FREND1_MASK);
+  data[0] = (uint8_t)cfg & CC1101_REG_RW_FREND1_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_FREND1, data, 2);
 }
 
 uint32_t cc1101_get_fscal(void)
@@ -639,13 +664,16 @@ uint32_t cc1101_get_fscal(void)
 
 void cc1101_set_fscal(uint32_t cal)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_FSCAL0, cal & CC1101_REG_RW_FSCAL0_MASK);
+  uint8_t data[4];
+  data[3] = (uint8_t)cal & CC1101_REG_RW_FSCAL0_MASK;
   cal = cal >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_FSCAL1, cal & CC1101_REG_RW_FSCAL1_MASK);
+  data[2] = (uint8_t)cal & CC1101_REG_RW_FSCAL1_MASK;
   cal = cal >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_FSCAL2, cal & CC1101_REG_RW_FSCAL2_MASK);
+  data[1] = (uint8_t)cal & CC1101_REG_RW_FSCAL2_MASK;
   cal = cal >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_FSCAL3, cal & CC1101_REG_RW_FSCAL3_MASK);
+  data[0] = (uint8_t)cal & CC1101_REG_RW_FSCAL3_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_FSCAL3, data, 4);
 }
 
 uint16_t cc1101_get_rcctrl(void)
@@ -661,9 +689,12 @@ uint16_t cc1101_get_rcctrl(void)
 
 void cc1101_set_rcctrl(uint16_t ctrl)
 {
-  cc1101_spi_write_register(CC1101_REG_RW_RCCTRL0, ctrl & CC1101_REG_RW_RCCTRL0_MASK);
+  uint8_t data[2];
+  data[1] = (uint8_t)ctrl & CC1101_REG_RW_RCCTRL0_MASK;
   ctrl = ctrl >> 8;
-  cc1101_spi_write_register(CC1101_REG_RW_RCCTRL1, ctrl & CC1101_REG_RW_RCCTRL1_MASK);
+  data[0] = (uint8_t)ctrl & CC1101_REG_RW_RCCTRL1_MASK;
+
+  cc1101_spi_write_register_burst(CC1101_REG_RW_RCCTRL1, data, 2);
 }