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authorChristian Pointner <equinox@mur.at>2015-02-19 01:41:48 (GMT)
committerChristian Pointner <equinox@mur.at>2015-02-19 01:41:48 (GMT)
commitd031f9e63d53cff9f8a50735a1c5ada9e3027637 (patch)
treeb8f2132fc19905c06954bc07cc26602b8fe8d402
parent57093dca01c30e74f784024640c6bdb43c2009d8 (diff)
hhd70dongle.old: reverted to older base
-rw-r--r--software/hhd70dongle.old/Makefile2
-rw-r--r--software/hhd70dongle.old/c1101lib.c517
-rw-r--r--software/hhd70dongle.old/c1101lib.h135
-rw-r--r--software/hhd70dongle.old/hhd70dongle.c44
4 files changed, 414 insertions, 284 deletions
diff --git a/software/hhd70dongle.old/Makefile b/software/hhd70dongle.old/Makefile
index fe926c2..1fea29b 100644
--- a/software/hhd70dongle.old/Makefile
+++ b/software/hhd70dongle.old/Makefile
@@ -45,8 +45,6 @@ LUFA_COMPONENTS := USB USBCLASS
include ../avr.include.mk
-CFLAGS += -D CC1101_QUARTZ_26M
-
program0: RESET_PARAM:=/dev/ttyACM0
program0: program
diff --git a/software/hhd70dongle.old/c1101lib.c b/software/hhd70dongle.old/c1101lib.c
index 209ccee..c24c398 100644
--- a/software/hhd70dongle.old/c1101lib.c
+++ b/software/hhd70dongle.old/c1101lib.c
@@ -31,178 +31,198 @@
*
*/
#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
#include <avr/io.h>
#include <util/delay.h>
#include "c1101lib.h"
-#include "cc1101_defines.h"
#include "hhd70.h"
#include "util.h"
-// internal functions
+/**** Helper Functions ****/
-#define CC1101_MAX_WAIT_RDY 21
+#define SPIC1101_MAX_WAIT 21
-static int16_t c1101_spi_write_byte_ok_get_status(uint8_t data)
+
+
+/* ###### ######
+ LUFA Library
+ Copyright (C) Dean Camera, 2012.
+
+ dean [at] fourwalledcubicle [dot] com
+ www.lufa-lib.org
+*/
+//#include <LUFA/Drivers/Misc/RingBuffer.h>
+#include <LUFA/Drivers/USB/USB.h>
+
+ /* Global I/O Buffers: */
+//static RingBuffer_t SPItoUSB_Buffer;
+//static uint8_t SPItoUSB_Buffer_Data[8];
+
+
+int16_t c1101_spi_write_byte_ok_get_status(char data)
{
- uint8_t sb;
- unsigned int attempts = 0;
- do
- {
- sb = hhd70_spi_exchange_byte(data);
+ //~ uint8_t debug_sb[6];
+ char sb;
+ unsigned int attempts = 0;
+ do
+ {
+ sb = hhd70_spi_exchange_byte(data);
//Note: content of returned StatusByte is actually context depenedant on sent command
// i.e. we won't get Fifo Byte count or overflow status on normal command and so on
// e.g. we only get TX Fifo Free Byte count while writing to TX Fifo
// thus it makes sense to only check for CHIP_RDY here
- if (attempts++ > CC1101_MAX_WAIT_RDY)
- return -1;
- } while (CC1101_STATUS_CHIP_NOT_RDY(sb));
- return sb;
+ //~ ((uint8_t*)"spi byte exchanged ",255);
+ //~ debug_sprint_int16hex(debug_sb, sb);
+ //~ (debug_sb,255);
+ if (attempts++ > SPIC1101_MAX_WAIT)
+ return -1;
+ } while ( SPIC1101_SB_CHIP_NOT_RDY(sb) );
+ return sb;
}
-int16_t c1101_spi_strobe_command(uint8_t cmd)
+int16_t c1101_spi_strobe_command(char address)
{
- if(cmd < CC1101_CMD_MIN || cmd > CC1101_CMD_MAX)
- return -1;
-
- hhd70_spi_cs_enable();
- hhd70_c1101_wait_chip_rdy();
- uint8_t rbyte = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_COMMAND | cmd);
- if(rbyte < 0)
- return -1;
- hhd70_spi_cs_disable();
- return rbyte;
+ char rbyte;
+ if (address < 0x30)
+ return -1;
+ hhd70_spi_cs_enable();
+ hhd70_c1101_wait_chip_rdy();
+ //POST DEBUG: don't return anything
+ rbyte = c1101_spi_write_byte_ok_get_status(address);
+ if (rbyte < 0)
+ return -1;
+ hhd70_spi_cs_disable();
+ return rbyte;
}
-int16_t c1101_spi_read_register(uint8_t addr)
+// note addresses range from 0x00 to 0x2F for normal registers and 0xF0 to 0xFD for special status registers
+int16_t c1101_spi_read_register(char address)
{
- if(addr > CC1101_ADDR_MAX)
- return -1;
-
- if(addr > CC1101_REG_RW_MAX)
- addr |= CC1101_HEADER_READONLY;
- else
- addr |= CC1101_HEADER_READ;
-
- hhd70_spi_cs_enable();
- hhd70_c1101_wait_chip_rdy();
- if(c1101_spi_write_byte_ok_get_status(addr) < 0)
- return -1;
- uint8_t rbyte = hhd70_spi_read_byte();
- hhd70_spi_cs_disable();
- return rbyte;
+ char rbyte;
+ if (address < 0x30)
+ address |= 0x80;
+ else
+ address |= 0xC0;
+ hhd70_spi_cs_enable();
+ hhd70_c1101_wait_chip_rdy();
+ if (c1101_spi_write_byte_ok_get_status(address) < 0)
+ return -1;
+ rbyte = hhd70_spi_read_byte();
+ hhd70_spi_cs_disable();
+ return rbyte;
}
-int16_t c1101_spi_write_register(uint8_t addr, uint8_t byte)
+// note addresses range from 0x00 to 0x2F for normal registers
+int16_t c1101_spi_write_register(char address, char byte)
{
- if(addr > CC1101_REG_RW_MAX)
- return -1;
-
- hhd70_spi_cs_enable();
- hhd70_c1101_wait_chip_rdy();
- if(c1101_spi_write_byte_ok_get_status(CC1101_HEADER_WRITE | addr) < 0)
- return -1;
- _delay_ms(2); // TODO: why wait here???
- if(c1101_spi_write_byte_ok_get_status(byte) < 0)
- return -1;
- hhd70_spi_cs_disable();
- return 1;
+ hhd70_spi_cs_enable();
+ hhd70_c1101_wait_chip_rdy();
+ if (c1101_spi_write_byte_ok_get_status(address & 0x3F) < 0)
+ return -1;
+ _delay_ms(2);
+ if (c1101_spi_write_byte_ok_get_status(byte) < 0)
+ return -1;
+ hhd70_spi_cs_disable();
+ return 1;
}
-void c1101_spi_dump_registers(void)
+void c1101_spi_dump_registers_to_usb(void)
{
- int c = 0;
- char debug_sb[6];
- hhd70_spi_cs_enable();
- hhd70_c1101_wait_chip_rdy();
- if (c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | 0x00) < 0)
- return;
- printf("dump all 46 registers:\r\n");
- for (c = 0; c < CC1101_REG_RW_MAX; c++) {
- debug_sprint_int16hex(debug_sb, hhd70_spi_read_byte());
- printf("%s", debug_sb);
- printf("\r\n");
- }
- hhd70_spi_cs_disable();
+ int c = 0;
+ char debug_sb[6];
+ hhd70_spi_cs_enable();
+ hhd70_c1101_wait_chip_rdy();
+ if (c1101_spi_write_byte_ok_get_status(0xC0) < 0)
+ return;
+ printf("dump all 46 registers:\r\n");
+ for (c=0; c<47; c++)
+ {
+ debug_sprint_int16hex(debug_sb, hhd70_spi_read_byte());
+ printf("%s", debug_sb);
+ printf("\r\n");
+ }
+ hhd70_spi_cs_disable();
}
-int c1101_spi_read_rxfifo(int leave_num_bytes, uint8_t *buffer, int maxlen)
+int c1101_spi_read_rxfifo(int leave_num_bytes, char *buffer, int maxlen)
{
- int num_read = 0;
- uint8_t num_available = 0;
- hhd70_spi_cs_enable();
- hhd70_c1101_wait_chip_rdy();
- if (c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READONLY | CC1101_REG_RO_RXBYTES) < 0)
- return -1;
-
- num_available = hhd70_spi_read_byte();
- if (num_available == 0)
- return 0;
- if (c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | CC1101_REG_FIFO) < 0)
- return -1;
- while (maxlen-- > 0 && num_available - num_read > leave_num_bytes)
- buffer[num_read++] = hhd70_spi_read_byte();
-
- hhd70_spi_cs_disable();
- return num_read;
+ int num_read = 0;
+ uint8_t num_available = 0;
+ hhd70_spi_cs_enable();
+ hhd70_c1101_wait_chip_rdy();
+ if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_RXBYTES) < 0)
+ return -1;
+ num_available = hhd70_spi_read_byte();
+ if (num_available == 0)
+ return 0;
+ if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST) < 0)
+ return -1;
+ while (maxlen-- > 0 && num_available - num_read > leave_num_bytes)
+ {
+ buffer[num_read++] = hhd70_spi_read_byte();
+ }
+ hhd70_spi_cs_disable();
+ return num_read;
}
//note: currently this function reads at most 15 bytes
-int c1101_spi_read_rxfifo_max15(int leave_num_bytes, uint8_t *buffer, int maxlen)
-{
- int16_t sb;
- int num_read = 0;
- hhd70_spi_cs_enable();
- hhd70_c1101_wait_chip_rdy();
- sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | CC1101_REG_FIFO);
- if (sb < 0)
- return -1;
- //note if CC1101_STATUS_FIFO_BYTES_AVAILABLE(sb) == 15 then 15 or more bytes are available
- while (maxlen-- > 0 && CC1101_STATUS_FIFO_BYTES_AVAILABLE(sb) - num_read > leave_num_bytes) {
+int c1101_spi_read_rxfifo_max15(int leave_num_bytes, char *buffer, int maxlen)
+{
+ int16_t sb;
+ int num_read = 0;
+ hhd70_spi_cs_enable();
+ hhd70_c1101_wait_chip_rdy();
+ sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST);
+ if (sb < 0)
+ return -1;
+ //note if SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) == 15 then 15 or more bytes are available
+ while (maxlen-- > 0 && SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) - num_read > leave_num_bytes)
+ {
//hope this works !!
- buffer[num_read++] = hhd70_spi_read_byte();
- }
- hhd70_spi_cs_disable();
- return num_read;
+ buffer[num_read++] = hhd70_spi_read_byte();
+ }
+ hhd70_spi_cs_disable();
+ return num_read;
}
//note: always check if num_written returned == len given
-int c1101_spi_write_txfifo(uint8_t *buffer, int len)
-{
- uint8_t sb;
- int num_written = 0;
- hhd70_spi_cs_enable();
- hhd70_c1101_wait_chip_rdy();
- sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_READ | CC1101_HEADER_BURST | CC1101_REG_FIFO);
- if (sb < 0)
- return -1;
- while (len-- > 0 && CC1101_STATUS_FIFO_BYTES_AVAILABLE(sb) > 2) {
- sb = c1101_spi_write_byte_ok_get_status(buffer[num_written++]);
- }
- hhd70_spi_cs_disable();
- return num_written;
-}
-
-//patable muste be uint8_t array of length 8
+int c1101_spi_write_txfifo(char *buffer, int len)
+{
+ char sb;
+ int num_written = 0;
+ hhd70_spi_cs_enable();
+ hhd70_c1101_wait_chip_rdy();
+ sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_WRITE_BURST);
+ if (sb < 0)
+ return -1;
+ while (len-- > 0 && SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) > 2)
+ {
+ sb = c1101_spi_write_byte_ok_get_status(buffer[num_written++]);
+ }
+ hhd70_spi_cs_disable();
+ return num_written;
+}
+
+//patable muste be char array of length 8
int c1101_spi_write_patable(uint8_t const patable[])
{
- int16_t sb;
- int8_t len = 8;
- hhd70_spi_cs_enable();
- hhd70_c1101_wait_chip_rdy();
- sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_WRITE | CC1101_HEADER_BURST | CC1101_REG_PATABLE);
- if (sb < 0)
- return -1;
- while (len-- > 0) {
- sb = c1101_spi_write_byte_ok_get_status(*patable);
- patable++;
- }
- hhd70_spi_cs_disable();
- return sb;
+ int16_t sb;
+ int8_t len = 8;
+ hhd70_spi_cs_enable();
+ hhd70_c1101_wait_chip_rdy();
+ sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_PATABLE_WRITE_BURST);
+ if (sb < 0)
+ return -1;
+ while (len-- > 0)
+ {
+ sb = c1101_spi_write_byte_ok_get_status(*patable);
+ patable++;
+ }
+ hhd70_spi_cs_disable();
+ return sb;
}
+
static uint8_t const pa_table_values_[] = { 0x00, 0x30, 0x20, 0x10, 0x01, 0x02, 0x11, 0x03,
0x12, 0x04, 0x05, 0x13, 0x06, 0x07, 0x21, 0x14, 0x08, 0x09, 0x0A, 0x15,
0x0B, 0x31, 0x16, 0x0C, 0x0D, 0x0E, 0x17, 0x0F, 0x22, 0x18, 0x19, 0x1A,
@@ -218,70 +238,69 @@ static uint8_t const pa_table_values_[] = { 0x00, 0x30, 0x20, 0x10, 0x01, 0x02,
#define PA_TABLE_VALUES_MAX ((sizeof(pa_table_values_)/sizeof(uint8_t))-1)
static uint8_t ook_power_ = 83; // ==> 3F
-
/**** External Functions ****/
uint16_t c1101_setFSKDeviationFromCarrier(int8_t m, int8_t e)
{
- c1101_spi_write_register(CC1101_REG_RW_DEVIATN, (m & 0x7) | ((e & 0x7) << 4));
+ c1101_spi_write_register(SPIC1101_ADDR_DEVIATN, (m & 0x7) | ((e & 0x7) << 4));
return (1983u * (8u+((uint32_t)m)) * (1u << ((uint32_t)e))) / 100; //return +- deviation in 10Hz Steps
}
void c1101_init(void)
{
//reset C1101
- c1101_spi_strobe_command(CC1101_CMD_SRES);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
_delay_ms(100);
//flush FIFOs
- c1101_spi_strobe_command(CC1101_CMD_SFRX);
- c1101_spi_strobe_command(CC1101_CMD_SFTX);
- //dump pre-init default values to stdout
- c1101_spi_dump_registers();
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
+ //dump pre-init default values to usb
+ c1101_spi_dump_registers_to_usb();
//enable analog temperature sensor on GDO0
- c1101_spi_write_register(CC1101_REG_RW_IOCFG0, 0x80);
+ c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x80);
//enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO)
- c1101_spi_write_register(CC1101_REG_RW_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
+ c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
// FIFOTHR RX FIFO and TX FIFO Thresholds
// pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx)
- //c1101_spi_write_register(CC1101_REG_RW_FIFOTHR, 2); //assert at 12 bytes in RX Fifo and 53 in TX Fifo
- c1101_spi_write_register(CC1101_REG_RW_FIFOTHR, 0); //assert at 4 bytes in RX Fifo and 61 in TX Fifo
+ //c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 2); //assert at 12 bytes in RX Fifo and 53 in TX Fifo
+ c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 0); //assert at 4 bytes in RX Fifo and 61 in TX Fifo
// PKTCTRL0 Packet Automation Control
- //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode
- c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
- //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000101); //crc enabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
- c1101_spi_write_register(CC1101_REG_RW_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet
+ //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode
+ c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+ //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000101); //crc enabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+ c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet
// FSCTRL1 Frequency Synthesizer Control
- c1101_spi_write_register(CC1101_REG_RW_FSCTRL1, 0x06);
+ c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, 0x06);
// FREQn Frequency Control Words
- c1101_spi_write_register(CC1101_REG_RW_FREQ2, 0x10); //should be 435.125 mhz
- c1101_spi_write_register(CC1101_REG_RW_FREQ1, 0xBF);
- c1101_spi_write_register(CC1101_REG_RW_FREQ0, 0xEF);
- c1101_spi_write_register(CC1101_REG_RW_FSCTRL0, 0); //frequency offset
+ c1101_spi_write_register(SPIC1101_ADDR_FREQ2, 0x10); //should be 435.125 mhz
+ c1101_spi_write_register(SPIC1101_ADDR_FREQ1, 0xBF);
+ c1101_spi_write_register(SPIC1101_ADDR_FREQ0, 0xEF);
+ c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, 0); //frequency offset
// MDMCFGn Modem Configuration
- c1101_spi_write_register(CC1101_REG_RW_MDMCFG4, 0xF8);
- c1101_spi_write_register(CC1101_REG_RW_MDMCFG3, 0x83);
- c1101_spi_write_register(CC1101_REG_RW_MDMCFG2, 0x12); //gfsk, 15/16 sync word
- c1101_spi_write_register(CC1101_REG_RW_MDMCFG1, 0x00);
+ c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4, 0xF8);
+ c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3, 0x83);
+ c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2, 0x12); //gfsk, 15/16 sync word
+ c1101_spi_write_register(SPIC1101_ADDR_MDMCFG1, 0x00);
//Sync Word
- c1101_spi_write_register(CC1101_REG_RW_SYNC1, 0x21);
- c1101_spi_write_register(CC1101_REG_RW_SYNC0, 0x42);
+ c1101_spi_write_register(SPIC1101_ADDR_SYNC1, 0x21);
+ c1101_spi_write_register(SPIC1101_ADDR_SYNC0, 0x42);
// DEVIATN Modem Deviation Setting
- c1101_spi_write_register(CC1101_REG_RW_DEVIATN, 0x11); //0x11 equals deviation of 3.5kHz; 0x27 equals deviation of 11.9kHz
+ c1101_spi_write_register(SPIC1101_ADDR_DEVIATN, 0x11); //0x11 equals deviation of 3.5kHz; 0x27 equals deviation of 11.9kHz
// MCSM0 Main Radio Control State Machine Configuration
- c1101_spi_write_register(CC1101_REG_RW_MCSM0, 0x18);
- c1101_spi_write_register(CC1101_REG_RW_MCSM1, 0b00111100); // State RX after recieving packet-> stay in RX; State TX after sending packet -> IDLE
+ c1101_spi_write_register(SPIC1101_ADDR_MCSM0, 0x18);
+ c1101_spi_write_register(SPIC1101_ADDR_MCSM1, 0b00111100); // State RX after recieving packet-> stay in RX; State TX after sending packet -> IDLE
// FOCCFG Frequency Offset Compensation Configuration
- c1101_spi_write_register(CC1101_REG_RW_FOCCFG, 0x16);
+ c1101_spi_write_register(SPIC1101_ADDR_FOCCFG, 0x16);
// WORCTRL Wake On Radio Control
- c1101_spi_write_register(CC1101_REG_RW_WORCTRL, 0xFB);
+ c1101_spi_write_register(SPIC1101_ADDR_WORCTRL, 0xFB);
// FSCALn Frequency Synthesizer Calibration
- c1101_spi_write_register(CC1101_REG_RW_FSCAL3, 0xE9);
- c1101_spi_write_register(CC1101_REG_RW_FSCAL2, 0x2A);
- c1101_spi_write_register(CC1101_REG_RW_FSCAL1, 0x00);
- c1101_spi_write_register(CC1101_REG_RW_FSCAL0, 0x1F);
+ c1101_spi_write_register(SPIC1101_ADDR_FSCAL3, 0xE9);
+ c1101_spi_write_register(SPIC1101_ADDR_FSCAL2, 0x2A);
+ c1101_spi_write_register(SPIC1101_ADDR_FSCAL1, 0x00);
+ c1101_spi_write_register(SPIC1101_ADDR_FSCAL0, 0x1F);
//FREN0 TX Power:
- c1101_spi_write_register(CC1101_REG_RW_FREND0, 0x10); //should be set using RF-Studio !!, for now, only use PA-Table Entry[0] no power ramping !! (FIXME: but should maybe be used)
- c1101_spi_write_register(CC1101_REG_PATABLE, 0xC0); //write PATABLE[0] only, rest needs to be written in Burst-Mode ! set to max power 10dBm
+ c1101_spi_write_register(SPIC1101_ADDR_FREND0, 0x10); //should be set using RF-Studio !!, for now, only use PA-Table Entry[0] no power ramping !! (FIXME: but should maybe be used)
+ c1101_spi_write_register(SPIC1101_ADDR_PATABLE_WRITE, 0xC0); //write PATABLE[0] only, rest needs to be written in Burst-Mode ! set to max power 10dBm
// note: for now: assume f_xosc to be 26 Mhz
// for ~433.125 Mhz -> freq = 1091741, freq_offset = 0
@@ -322,15 +341,15 @@ void c1101_init_w_rfstudiosettings1(void)
// Rf settings for CC1101
//
//reset C1101
- c1101_spi_strobe_command(CC1101_CMD_SRES);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
_delay_ms(100);
//flush FIFOs
- c1101_spi_strobe_command(CC1101_CMD_SFRX);
- c1101_spi_strobe_command(CC1101_CMD_SFTX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
//enable analog temperature sensor on GDO0
- c1101_spi_write_register(CC1101_REG_RW_IOCFG0, 0x80);
+ c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x80);
//enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO)
- c1101_spi_write_register(CC1101_REG_RW_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
+ c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
//Values from SmartRFStudio:
c1101_spi_write_patable(pa_table);
@@ -363,41 +382,41 @@ void c1101_init_ook_beacon(void)
// PA table by TI
//reset C1101
- c1101_spi_strobe_command(CC1101_CMD_SRES);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SRES);
_delay_ms(100);
//flush FIFOs
- c1101_spi_strobe_command(CC1101_CMD_SFRX);
- c1101_spi_strobe_command(CC1101_CMD_SFTX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
//
// Rf settings for CC1101
//
- c1101_spi_write_register(CC1101_REG_RW_IOCFG0, 0x00);
+ c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x00);
//enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO)
- c1101_spi_write_register(CC1101_REG_RW_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
+ c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0x41 ); //0x40, 0x42, 0x44, 0x47
// pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx)
- //c1101_spi_write_register(CC1101_REG_RW_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
- c1101_spi_write_register(CC1101_REG_RW_FIFOTHR, 0); //assert at 4 bytes in RX Fifo and 61 in TX Fifo
- //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0,0x12);//Packet Automation Control
- //c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
- c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000110001); //crc disabled; asynchronous serial input on GDO0
- c1101_spi_write_register(CC1101_REG_RW_FSCTRL1,0x06); //Frequency Synthesizer Control
- c1101_spi_write_register(CC1101_REG_RW_FREQ2,0x10); //Frequency Control Word, High Byte
- c1101_spi_write_register(CC1101_REG_RW_FREQ1,0xD3); //Frequency Control Word, Middle Byte
- c1101_spi_write_register(CC1101_REG_RW_FREQ0,0xF0); //Frequency Control Word, Low Byte
- c1101_spi_write_register(CC1101_REG_RW_MDMCFG4,0xF5); //Modem Configuration
- c1101_spi_write_register(CC1101_REG_RW_MDMCFG3,0x43); //Modem Configuration
- c1101_spi_write_register(CC1101_REG_RW_MDMCFG2,0x30); //Modem Configuration
- c1101_spi_write_register(CC1101_REG_RW_MDMCFG1,0x00); //Modem Configuration
- c1101_spi_write_register(CC1101_REG_RW_DEVIATN,0x07); //Modem Deviation Setting
- c1101_spi_write_register(CC1101_REG_RW_MCSM0,0x18); //Main Radio Control State Machine Configuration
- c1101_spi_write_register(CC1101_REG_RW_FOCCFG,0x16); //Frequency Offset Compensation Configuration
- c1101_spi_write_register(CC1101_REG_RW_WORCTRL,0xFB); //Wake On Radio Control
- c1101_spi_write_register(CC1101_REG_RW_FREND0,0x11); //Front End TX Configuration // PA_POWER[2:0] = 1
- c1101_spi_write_register(CC1101_REG_RW_FSCAL3,0xE9); //Frequency Synthesizer Calibration
- c1101_spi_write_register(CC1101_REG_RW_FSCAL2,0x2A); //Frequency Synthesizer Calibration
- c1101_spi_write_register(CC1101_REG_RW_FSCAL1,0x00); //Frequency Synthesizer Calibration
- c1101_spi_write_register(CC1101_REG_RW_FSCAL0,0x1F); //Frequency Synthesizer Calibration
+ //c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR,0x47); //RX FIFO and TX FIFO Thresholds
+ c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 0); //assert at 4 bytes in RX Fifo and 61 in TX Fifo
+ //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0,0x12);//Packet Automation Control
+ //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+ c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000110001); //crc disabled; asynchronous serial input on GDO0
+ c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1,0x06); //Frequency Synthesizer Control
+ c1101_spi_write_register(SPIC1101_ADDR_FREQ2,0x10); //Frequency Control Word, High Byte
+ c1101_spi_write_register(SPIC1101_ADDR_FREQ1,0xD3); //Frequency Control Word, Middle Byte
+ c1101_spi_write_register(SPIC1101_ADDR_FREQ0,0xF0); //Frequency Control Word, Low Byte
+ c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4,0xF5); //Modem Configuration
+ c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3,0x43); //Modem Configuration
+ c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2,0x30); //Modem Configuration
+ c1101_spi_write_register(SPIC1101_ADDR_MDMCFG1,0x00); //Modem Configuration
+ c1101_spi_write_register(SPIC1101_ADDR_DEVIATN,0x07); //Modem Deviation Setting
+ c1101_spi_write_register(SPIC1101_ADDR_MCSM0,0x18); //Main Radio Control State Machine Configuration
+ c1101_spi_write_register(SPIC1101_ADDR_FOCCFG,0x16); //Frequency Offset Compensation Configuration
+ c1101_spi_write_register(SPIC1101_ADDR_WORCTRL,0xFB); //Wake On Radio Control
+ c1101_spi_write_register(SPIC1101_ADDR_FREND0,0x11); //Front End TX Configuration // PA_POWER[2:0] = 1
+ c1101_spi_write_register(SPIC1101_ADDR_FSCAL3,0xE9); //Frequency Synthesizer Calibration
+ c1101_spi_write_register(SPIC1101_ADDR_FSCAL2,0x2A); //Frequency Synthesizer Calibration
+ c1101_spi_write_register(SPIC1101_ADDR_FSCAL1,0x00); //Frequency Synthesizer Calibration
+ c1101_spi_write_register(SPIC1101_ADDR_FSCAL0,0x1F); //Frequency Synthesizer Calibration
c1101_ook_power_set(ook_power_);
hhd70_config_GDO0_OOK_output(true);
@@ -440,81 +459,81 @@ void c1101_ook_power_dec()
void c1101_permanently_save_current_rx_tx_freqoffset_auto_compensation()
{
int16_t freq_offset;
- freq_offset = c1101_spi_read_register(CC1101_REG_RO_FREQUEST);
+ freq_offset = c1101_spi_read_register(SPIC1101_ADDR_FREQUEST);
if (freq_offset >= 0)
{
- c1101_spi_write_register(CC1101_REG_RW_FSCTRL0, (uint8_t) freq_offset);
+ c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, (uint8_t) freq_offset);
}
}
// WARNING: All content of the PATABLE except for the first byte (index 0) is lost when entering the SLEEP state.
-uint8_t c1101_putToSleep(void)
+char c1101_putToSleep(void)
{
- return c1101_spi_strobe_command(CC1101_CMD_SPWD);
+ return c1101_spi_strobe_command(SPIC1101_ADDR_SPWD);
}
uint16_t c1101_measureTemp(void)
{
uint16_t temp;
- uint8_t ptest_value=0x7F;
- ptest_value = c1101_spi_read_register(CC1101_REG_RW_PTEST);
- c1101_spi_write_register(CC1101_REG_RW_PTEST, 0xBF);
+ char ptest_value=0x7F;
+ ptest_value = c1101_spi_read_register(SPIC1101_ADDR_PTEST);
+ c1101_spi_write_register(SPIC1101_ADDR_PTEST, 0xBF);
_delay_ms(5);
temp = adc_read(ADCMUX_INTERNALTEMP);
- c1101_spi_write_register(CC1101_REG_RW_PTEST, ptest_value);
+ c1101_spi_write_register(SPIC1101_ADDR_PTEST, ptest_value);
return temp;
}
-void c1101_handleMARCStatusByte(uint8_t sb)
+void c1101_handleMARCStatusByte(char sb)
{
//on RXFifo Overflow, Flush RX Fifo
if (sb == 0x11)
{
- c1101_spi_strobe_command(CC1101_CMD_SFRX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
printf("RX fifo flushed\r\n");
}
//on TXFifo Overflow, Flush TX Fifo
else if (sb == 0x16)
{
- c1101_spi_strobe_command(CC1101_CMD_SFTX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
printf("TX fifo flushed\r\n");
}
}
-void c1101_handleStatusByte(uint8_t sb)
+void c1101_handleStatusByte(char sb)
{
//on RXFifo Overflow, Flush RX Fifo
- if (CC1101_STATUS_RXFIFO_OVERFLOW(sb))
+ if (SPIC1101_SB_RXFIFO_OVERFLOW(sb))
{
- c1101_spi_strobe_command(CC1101_CMD_SFRX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFRX);
printf("RX fifo flushed\r\n");
}
//on TXFifo Overflow, Flush TX Fifo
- if (CC1101_STATUS_TXFIFO_OVERFLOW(sb))
+ if (SPIC1101_SB_TXFIFO_OVERFLOW(sb))
{
- c1101_spi_strobe_command(CC1101_CMD_SFTX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
printf("TX fifo flushed\r\n");
}
}
-uint8_t c1101_getStatus(void)
+char c1101_getStatus(void)
{
- uint8_t sb=0;
+ char sb=0;
hhd70_spi_cs_enable();
hhd70_c1101_wait_chip_rdy();
- sb = c1101_spi_write_byte_ok_get_status(CC1101_HEADER_COMMAND | CC1101_CMD_SNOP);
+ sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_SNOP);
hhd70_spi_cs_disable();
c1101_handleStatusByte(sb);
return sb;
}
-uint8_t c1101_getMARCState(void)
+char c1101_getMARCState(void)
{
- uint8_t sb=0;
- sb = c1101_spi_read_register(CC1101_REG_RO_MARCSTATE);
+ char sb=0;
+ sb = c1101_spi_read_register(SPIC1101_ADDR_MARCSTATE);
sb &= 0x1F;
//debug start
- /* uint8_t debug_sb[6]; */
+ /* char debug_sb[6]; */
/* printf("c1101 MARCState:\r\n"); */
/* debug_sprint_int16hex(debug_sb, sb); */
/* printf("%s", debug_sb); */
@@ -525,7 +544,7 @@ uint8_t c1101_getMARCState(void)
uint8_t c1101_getNumBytesInTXFifo(void)
{
- return c1101_spi_read_register(CC1101_REG_RO_TXBYTES);
+ return c1101_spi_read_register(SPIC1101_ADDR_TXBYTES);
}
@@ -536,7 +555,7 @@ bool c1101_waitUntilIDLEState(uint16_t timeout_ms)
for (uint16_t c = 0; c < timeout_ms; c++)
{
sb = c1101_getStatus();
- if (CC1101_STATUS_IDLE(sb))
+ if (SPIC1101_SB_IDLE(sb))
return true;
_delay_ms(1);
}
@@ -578,23 +597,23 @@ bool c1101_writeFrequencyRegisters(uint32_t freq)
if (! c1101_waitUntilIDLEState(2000)) //wait 2sec max
return false;
//programm frequency
- c1101_spi_write_register(CC1101_REG_RW_FREQ0, freq & 0xFF);
- c1101_spi_write_register(CC1101_REG_RW_FREQ1, (freq >> 8) & 0xFF);
- c1101_spi_write_register(CC1101_REG_RW_FREQ2, (freq >> 16) & 0x3F);
+ c1101_spi_write_register(SPIC1101_ADDR_FREQ0, freq & 0xFF);
+ c1101_spi_write_register(SPIC1101_ADDR_FREQ1, (freq >> 8) & 0xFF);
+ c1101_spi_write_register(SPIC1101_ADDR_FREQ2, (freq >> 16) & 0x3F);
//set channel 0
- c1101_spi_write_register(CC1101_REG_RW_CHANNR, 0);
+ c1101_spi_write_register(SPIC1101_ADDR_CHANNR, 0);
return true;
}
uint32_t c1101_readFrequencyRegisters(void)
{
uint32_t freq = 0;
- freq = ((uint8_t) c1101_spi_read_register(CC1101_REG_RW_FREQ2)) & 0x3F;
+ freq = ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ2)) & 0x3F;
freq = freq << 8;
- freq |= ((uint8_t) c1101_spi_read_register(CC1101_REG_RW_FREQ1));
+ freq |= ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ1));
freq = freq << 8;
- freq |= ((uint8_t) c1101_spi_read_register(CC1101_REG_RW_FREQ0));
+ freq |= ((uint8_t) c1101_spi_read_register(SPIC1101_ADDR_FREQ0));
return freq;
}
@@ -602,7 +621,7 @@ uint32_t c1101_readFrequencyRegisters(void)
// freq: desired_carrier_freq [Hz] *2^16 / f_XOSC
bool c1101_setFrequency(uint32_t freq_hz)
{
- uint32_t freq = (uint32_t)((float)freq_hz / CC1101_FREQ_CORR);
+ uint32_t freq = (uint32_t)((float)freq_hz / C1101_FREQ_TO_HZ);
if ( freq <= 0x3FFFFF)
return c1101_writeFrequencyRegisters(freq);
else
@@ -613,7 +632,7 @@ bool c1101_setFrequency(uint32_t freq_hz)
// freq: desired_carrier_freq [Hz] *2^16 / f_XOSC
bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz)
{
- int32_t freq_change = (int32_t)((float)freq_change_hz / CC1101_FREQ_CORR);
+ int32_t freq_change = (int32_t)((float)freq_change_hz / C1101_FREQ_TO_HZ);
int32_t freq = (int32_t) c1101_readFrequencyRegisters();
freq += freq_change;
@@ -626,7 +645,7 @@ bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz)
uint32_t c1101_getCurrentCarrierFrequencyHz(void)
{
- return (uint32_t)((float)c1101_readFrequencyRegisters() * CC1101_FREQ_CORR);
+ return (uint32_t)((float)c1101_readFrequencyRegisters() * C1101_FREQ_TO_HZ);
}
// if_freq: desired intermidiate rx frequency [Hz] *2^10 / f_XOSC
@@ -637,22 +656,22 @@ bool c1101_setIFFrequency(uint32_t freq_hz)
if (! c1101_waitUntilIDLEState(2000)) //wait 2sec max
return false;
- c1101_spi_write_register(CC1101_REG_RW_FSCTRL1, if_freq & 0x1F);
+ c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, if_freq & 0x1F);
return true;
}
-bool c1101_transmitData(uint8_t *buffer, uint8_t len)
+bool c1101_transmitData(char *buffer, uint8_t len)
{
//~ uint8_t debug_sb[6];
uint8_t num_written = 0;
bool success = true;
- //~ uint8_t mcsm1 = c1101_spi_read_register(CC1101_REG_RW_MCSM1);
+ //~ uint8_t mcsm1 = c1101_spi_read_register(SPIC1101_ADDR_MCSM1);
//~ //configure state machine to automatically go to IDLE, once packet was transmitted
//~ mcsm1 = (mcsm1 & 0b11111100) | 0b00;
- //~ c1101_spi_write_register(CC1101_REG_RW_MCSM1, 0x18);
- //~ c1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
+ //~ c1101_spi_write_register(SPIC1101_ADDR_MCSM1, 0x18);
+ //~ c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length)
// flush TX FIFO
- c1101_spi_strobe_command(CC1101_CMD_SFTX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SFTX);
//~ //fill buffer
//~ num_written = c1101_spi_write_txfifo(buffer, len);
@@ -672,8 +691,8 @@ bool c1101_transmitData(uint8_t *buffer, uint8_t len)
//~ (debug_sb,255);
//start transmitting
- //num_written = c1101_spi_strobe_command(CC1101_CMD_STX);
- //~ num_written = hhd70_spi_exchange_byte(CC1101_CMD_STX);
+ //num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX);
+ //~ num_written = hhd70_spi_exchange_byte(SPIC1101_ADDR_STX);
//~ ((uint8_t*)"Strobe STX",255);
//~ debug_sprint_int16hex(debug_sb, num_written);
//~ (debug_sb,255);
@@ -696,7 +715,7 @@ bool c1101_transmitData(uint8_t *buffer, uint8_t len)
goto c1101_transmitData_cleanup;
}
//from state IDLE or RX go to TX
- num_written = c1101_spi_strobe_command(CC1101_CMD_STX);
+ num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX);
//~ ((uint8_t*)"TX2 num written",255);
//~ debug_sprint_int16hex(debug_sb, num_written);
@@ -723,10 +742,10 @@ bool c1101_transmitData(uint8_t *buffer, uint8_t len)
return success;
}
-void c1101_transmitData_infPktMode(uint8_t *buffer, uint8_t len)
+void c1101_transmitData_infPktMode(char *buffer, uint8_t len)
{
//in infinite Packet Mode, prepend length to buffer:
- uint8_t *new_buffer = malloc(len+1);
+ char *new_buffer = malloc(len+1);
new_buffer[0] = len;
memcpy(new_buffer+1, buffer, len);
//variable packet length: write length of packet to TX FIFO:
@@ -737,7 +756,7 @@ void c1101_transmitData_infPktMode(uint8_t *buffer, uint8_t len)
void c1101_recieveData(void)
{
uint8_t const max_len=255;
- uint8_t recv_data[256];
+ char recv_data[256];
uint8_t num_recv = 0;
uint8_t num_recv_total = 0;
uint8_t num_leave_in_fifo = 1;
@@ -758,7 +777,7 @@ void c1101_recieveData(void)
}
//max returned: 64 bytes
-int c1101_readRXFifo(uint8_t *buffer)
+int c1101_readRXFifo(char *buffer)
{
//check RXBYTES.NUM_RXBYTES
// never read more bytes than avaiblabe or we will read garbage
diff --git a/software/hhd70dongle.old/c1101lib.h b/software/hhd70dongle.old/c1101lib.h
index f24126b..e653a4b 100644
--- a/software/hhd70dongle.old/c1101lib.h
+++ b/software/hhd70dongle.old/c1101lib.h
@@ -30,42 +30,143 @@
* along with mur.sat. If not, see <http://www.gnu.org/licenses/>.
*
*/
-#ifndef MURSAT_c1101lib_h_INCLUDED
-#define MURSAT_c1101lib_h_INCLUDED
+#ifndef MURSAT_c1101lib_h_INCLUDED__
+#define MURSAT_c1101lib_h_INCLUDED__
+
+#define C1101_FIFO_MAX_LEN 64
#include <stdbool.h>
-// TODO: should be internal only...
-int16_t c1101_spi_read_register(uint8_t address);
-int16_t c1101_spi_write_register(uint8_t address, uint8_t byte);
-int16_t c1101_spi_strobe_command(uint8_t cmd);
+//read/write config registers:
+#define SPIC1101_ADDR_IOCFG2 0x00
+#define SPIC1101_ADDR_IOCFG1 0x01
+#define SPIC1101_ADDR_IOCFG0 0x02
+#define SPIC1101_ADDR_FIFOTHR 0x03
+#define SPIC1101_ADDR_SYNC1 0x04
+#define SPIC1101_ADDR_SYNC0 0x05
+#define SPIC1101_ADDR_PKTLEN 0x06
+#define SPIC1101_ADDR_PKTCTRL1 0x07
+#define SPIC1101_ADDR_PKTCTRL0 0x08
+#define SPIC1101_ADDR_ADDR 0x09
+#define SPIC1101_ADDR_CHANNR 0x0A
+#define SPIC1101_ADDR_FSCTRL1 0x0B
+#define SPIC1101_ADDR_FSCTRL0 0x0C
+#define SPIC1101_ADDR_FREQ2 0x0D
+#define SPIC1101_ADDR_FREQ1 0x0E
+#define SPIC1101_ADDR_FREQ0 0x0F
+#define SPIC1101_ADDR_MDMCFG4 0x10
+#define SPIC1101_ADDR_MDMCFG3 0x11
+#define SPIC1101_ADDR_MDMCFG2 0x12
+#define SPIC1101_ADDR_MDMCFG1 0x13
+#define SPIC1101_ADDR_MDMCFG0 0x14
+#define SPIC1101_ADDR_DEVIATN 0x15
+#define SPIC1101_ADDR_MCSM2 0x16
+#define SPIC1101_ADDR_MCSM1 0x17
+#define SPIC1101_ADDR_MCSM0 0x18
+#define SPIC1101_ADDR_FOCCFG 0x19
+#define SPIC1101_ADDR_BSCFG 0x1A
+#define SPIC1101_ADDR_AGCCTRL2 0x1B
+#define SPIC1101_ADDR_AGCCTRL1 0x1C
+#define SPIC1101_ADDR_AGCCTRL0 0x1D
+#define SPIC1101_ADDR_WOREVT1 0x1E
+#define SPIC1101_ADDR_WOREVT0 0x1F
+#define SPIC1101_ADDR_WORCTRL 0x20
+#define SPIC1101_ADDR_FREND1 0x21
+#define SPIC1101_ADDR_FREND0 0x22
+#define SPIC1101_ADDR_FSCAL3 0x23
+#define SPIC1101_ADDR_FSCAL2 0x24
+#define SPIC1101_ADDR_FSCAL1 0x25
+#define SPIC1101_ADDR_FSCAL0 0x26
+#define SPIC1101_ADDR_RCCTRL1 0x27
+#define SPIC1101_ADDR_RCCTRL0 0x28
+#define SPIC1101_ADDR_FSTEST 0x29
+#define SPIC1101_ADDR_PTEST 0x2A
+#define SPIC1101_ADDR_AGCTEST 0x2B
+#define SPIC1101_ADDR_TEST2 0x2C
+#define SPIC1101_ADDR_TEST1 0x2D
+#define SPIC1101_ADDR_TEST0 0x2E
+
+//commands:
+#define SPIC1101_ADDR_SRES 0x30
+#define SPIC1101_ADDR_SFSTXON 0x31
+#define SPIC1101_ADDR_SXOFF 0x32
+#define SPIC1101_ADDR_SCAL 0x33
+#define SPIC1101_ADDR_SRX 0x34
+#define SPIC1101_ADDR_STX 0x35
+#define SPIC1101_ADDR_SIDLE 0x36
+#define SPIC1101_ADDR_SWOR 0x38
+#define SPIC1101_ADDR_SPWD 0x39
+#define SPIC1101_ADDR_SFRX 0x3A
+#define SPIC1101_ADDR_SFTX 0x3B
+#define SPIC1101_ADDR_SWORRST 0x3C
+#define SPIC1101_ADDR_SNOP 0x3D
+
+//readonly registers:
+#define SPIC1101_ADDR_PARTNUM (0x30 | 0xC0)
+#define SPIC1101_ADDR_VERSION (0x31 | 0xC0)
+#define SPIC1101_ADDR_FREQUEST (0x32 | 0xC0)
+#define SPIC1101_ADDR_LQI (0x33 | 0xC0)
+#define SPIC1101_ADDR_RSSI (0x34 | 0xC0)
+#define SPIC1101_ADDR_MARCSTATE (0x35 | 0xC0)
+#define SPIC1101_ADDR_WORTIME1 (0x36 | 0xC0)
+#define SPIC1101_ADDR_WORTIME0 (0x37 | 0xC0)
+#define SPIC1101_ADDR_PKTSTATUS (0x38 | 0xC0)
+#define SPIC1101_ADDR_VCO_VC_DAC (0x39 | 0xC0)
+#define SPIC1101_ADDR_TXBYTES (0x3A | 0xC0)
+#define SPIC1101_ADDR_RXBYTES (0x3B | 0xC0)
+#define SPIC1101_ADDR_RCCTRL1_STATUS (0x3C | 0xC0)
+#define SPIC1101_ADDR_RCCTRL0_STATUS (0x3D | 0xC0)
+
+#define SPIC1101_ADDR_FIFO_READ (0x3F | 0x80)
+#define SPIC1101_ADDR_FIFO_READ_BURST (0x3F | 0x80 | 0xC0)
+#define SPIC1101_ADDR_FIFO_WRITE 0x3F
+#define SPIC1101_ADDR_FIFO_WRITE_BURST (0x3F | 0x40)
+
+#define SPIC1101_ADDR_PATABLE_READ (0x3E | 0x80)
+#define SPIC1101_ADDR_PATABLE_READ_BURST (0x3E | 0x80 | 0xC0)
+#define SPIC1101_ADDR_PATABLE_WRITE 0x3E
+#define SPIC1101_ADDR_PATABLE_WRITE_BURST (0x3E | 0x40)
+
+
+#define SPIC1101_SB_CHIP_NOT_RDY(x) (x & 0b10000000)
+#define SPIC1101_SB_IDLE(x) (x & 0b01110000) == 0
+#define SPIC1101_SB_RXMODE(x) (x & 0b01110000) == 0b0010000
+#define SPIC1101_SB_TXMODE(x) (x & 0b01110000) == 0b0100000
+#define SPIC1101_SB_FSTXON(x) (x & 0b01110000) == 0b0110000
+#define SPIC1101_SB_CALIBRATE(x) (x & 0b01110000) == 0b1000000
+#define SPIC1101_SB_SETTLING(x) (x & 0b01110000) == 0b1010000
+#define SPIC1101_SB_RXFIFO_OVERFLOW(x) (x & 0b01110000) == 0b1100000
+#define SPIC1101_SB_TXFIFO_OVERFLOW(x) (x & 0b01110000) == 0b1110000
+#define SPIC1101_SB_FIFO_BYTES_AVAILABLE(x) (x & 0b00001111)
+
+#define C1101_FREQ_TO_HZ 396.728515 // = Fosc/65536 = 26000000/65536
+int16_t c1101_spi_read_register(char address);
+int16_t c1101_spi_write_register(char address, char byte);
+int16_t c1101_spi_strobe_command(char address);
+
+uint16_t c1101_setFSKDeviationFromCarrier(int8_t m, int8_t e);
void c1101_init(void);
void c1101_init_ook_beacon(void);
-
uint8_t c1101_ook_power_get(void);
uint8_t c1101_ook_power_get_raw(void);
void c1101_ook_power_set(uint8_t power);
void c1101_ook_power_inc(void);
void c1101_ook_power_dec(void);
-
-void c1101_handleStatusByte(uint8_t sb);
-uint8_t c1101_getStatus(void);
-
+void c1101_handleStatusByte(char sb);
+char c1101_getStatus(void);
uint16_t c1101_measureTemp(void);
-void c1101_spi_dump_registers(void);
+void c1101_spi_dump_registers_to_usb(void);
void c1101_permanently_save_current_rx_tx_freqoffset_auto_compensation(void);
bool c1101_setFrequency(uint32_t freq_hz);
bool c1101_changeFrequencyByRelativeValue(int32_t freq_change_hz);
uint32_t c1101_getCurrentCarrierFrequencyHz(void);
bool c1101_setIFFrequency(uint32_t freq_hz);
-uint16_t c1101_setFSKDeviationFromCarrier(int8_t m, int8_t e);
-
-bool c1101_transmitData(uint8_t *buffer, uint8_t len);
-void c1101_transmitData_infPktMode(uint8_t *buffer, uint8_t len);
+bool c1101_transmitData(char *buffer, uint8_t len);
+void c1101_transmitData_infPktMode(char *buffer, uint8_t len);
void c1101_recieveData(void);
//max returned: 64 bytes
-int c1101_readRXFifo(uint8_t *buffer);
+int c1101_readRXFifo(char *buffer);
#endif
diff --git a/software/hhd70dongle.old/hhd70dongle.c b/software/hhd70dongle.old/hhd70dongle.c
index f28886d..31f511d 100644
--- a/software/hhd70dongle.old/hhd70dongle.c
+++ b/software/hhd70dongle.old/hhd70dongle.c
@@ -43,7 +43,6 @@
#include "hhd70.h"
#include "c1101lib.h"
-#include "cc1101_defines.h"
//todo: move to separte File:
@@ -71,6 +70,7 @@ char write_buffer[64]; // buffer for writing usb signals
bool enable_tx_part=false;
bool enable_rx_part=false;
bool enable_beacon_part=false;
+bool beacon_state=false;
void print_part_status(void)
{
@@ -96,12 +96,13 @@ void print_part_status(void)
void beacon_enable(void)
{
- c1101_spi_strobe_command(CC1101_CMD_STX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_STX);
hhd70_palna_txmode();
}
void beacon_on(void)
{
+ beacon_state = true;
hhd70_set_OOK_GDO0_high();
led_on();
}
@@ -110,12 +111,13 @@ void beacon_off(void)
{
led_off();
hhd70_set_OOK_GDO0_low();
+ beacon_state = false;
}
void beacon_disable(void)
{
hhd70_palna_rxmode();
- c1101_spi_strobe_command(CC1101_CMD_SIDLE);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SIDLE);
}
int main(void)
@@ -134,7 +136,7 @@ int main(void)
printf("hhd70dongle ready\r\n");
_delay_ms(500);
- c1101_spi_strobe_command(CC1101_CMD_SRES); // reset c1101
+ c1101_spi_strobe_command(SPIC1101_ADDR_SRES); // reset c1101
//c1101 init now happens after pressing B, S or E
hhd70_palna_rxmode();
@@ -171,7 +173,7 @@ int main(void)
enable_tx_part=false;
enable_rx_part=false;
enable_beacon_part=false;
- c1101_spi_strobe_command(CC1101_CMD_SRES); // reset c1101
+ c1101_spi_strobe_command(SPIC1101_ADDR_SRES); // reset c1101
hhd70_palna_rxmode();
print_part_status();
led_off();
@@ -214,7 +216,7 @@ int main(void)
}
else if ((char) recv_byte == 'R')
{
- c1101_spi_dump_registers();
+ c1101_spi_dump_registers_to_usb();
print_part_status();
}
else if ((char) recv_byte == 'D' || (char) recv_byte == 'd')
@@ -330,18 +332,28 @@ int main(void)
else if ((char) recv_byte == ' ')
{
if (enable_beacon_part) {
- hhd70_set_OOK_GDO0_toggle();
+ /* hhd70_set_OOK_GDO0_toggle(); */
+ if(beacon_state) {
+ beacon_state = false;
+ hhd70_set_OOK_GDO0_low();
+ led_off();
+ hhd70_palna_rxmode();
+ } else {
+ beacon_state = true;
+ hhd70_set_OOK_GDO0_high();
+ led_on();
+ hhd70_palna_txmode();
+ }
}
}
}
-
usbio_task();
if (enable_rx_part)
{
- c1101_spi_strobe_command(CC1101_CMD_SRX); // enter RX - Mode
+ c1101_spi_strobe_command(SPIC1101_ADDR_SRX); // enter RX - Mode
_delay_ms(1000);
if (hhd70_rx_data_available())
@@ -349,7 +361,7 @@ int main(void)
led_on();
printf("RX: GDO2 pin HIGH\r\n");
printf("c1101 rx bytes:");
- debug_sprint_int16hex(write_buffer, c1101_spi_read_register(CC1101_REG_RO_RXBYTES));
+ debug_sprint_int16hex(write_buffer, c1101_spi_read_register(SPIC1101_ADDR_RXBYTES));
printf("%s", write_buffer);
printf("\r\n");
c1101_recieveData();
@@ -357,15 +369,15 @@ int main(void)
}
printf("c1101 rssi: ");
- debug_sprint_int16hex(write_buffer, c1101_spi_read_register(CC1101_REG_RO_RSSI));
+ debug_sprint_int16hex(write_buffer, c1101_spi_read_register(SPIC1101_ADDR_RSSI));
printf("%s", write_buffer);
printf("\r\n");
printf("c1101 tx bytes: ");
- debug_sprint_int16hex(write_buffer, c1101_spi_read_register(CC1101_REG_RO_TXBYTES));
+ debug_sprint_int16hex(write_buffer, c1101_spi_read_register(SPIC1101_ADDR_TXBYTES));
printf("%s", write_buffer);
printf("\r\n");
printf("c1101 rx bytes: ");
- int16_t num_rx_bytes = c1101_spi_read_register(CC1101_REG_RO_RXBYTES);
+ int16_t num_rx_bytes = c1101_spi_read_register(SPIC1101_ADDR_RXBYTES);
debug_sprint_int16hex(write_buffer, num_rx_bytes);
printf("%s", write_buffer);
printf("\r\n");
@@ -409,7 +421,7 @@ int main(void)
/* _delay_ms(250); */
/* led_on(); */
/* printf("TX Data: String\r\n"); */
- /* c1101_transmitData_infPktMode("OE6EOF test mur.sat GFSK r:9k6 fdev:11kHz 1234567890123456789012345678901234567890 End of Test",93); */
+ c1101_transmitData_infPktMode("OE6EOF test mur.sat GFSK r:9k6 fdev:11kHz 1234567890123456789012345678901234567890 End of Test",93);
/* led_off(); */
/* _delay_ms(100); */
/* led_on(); */
@@ -425,12 +437,12 @@ int main(void)
led_on();
//c1101_transmitData_infPktMode(mursat_beacon,sizeof(mursat_beacon));
hhd70_palna_txmode();
- c1101_spi_strobe_command(CC1101_CMD_STX);
+ c1101_spi_strobe_command(SPIC1101_ADDR_STX);
hhd70_set_OOK_GDO0_high();
_delay_ms(1000);
led_off();
hhd70_set_OOK_GDO0_low();
- c1101_spi_strobe_command(CC1101_CMD_SIDLE);
+ c1101_spi_strobe_command(SPIC1101_ADDR_SIDLE);
hhd70_palna_rxmode();
_delay_ms(200);
}*/