/*
 *
 *  mur.sat
 *
 *  Somewhen in the year 2012, mur.at will have a nano satellite launched
 *  into a low earth orbit (310 km above the surface of our planet). The
 *  satellite itself is a TubeSat personal satellite kit, developed and
 *  launched by interorbital systems. mur.sat is a joint venture of mur.at,
 *  ESC im Labor and realraum.
 *
 *  Please visit the project hompage at sat.mur.at for further information.
 *
 *
 *  Copyright (C) 2012 Bernhard Tittelbach <xro@realraum.at>
 *
 *  This file is part of mur.sat.
 *
 *  mur.sat is free software: you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation, either version 3 of the License, or
 *  any later version.
 *
 *  mur.sat is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with mur.sat. If not, see <http://www.gnu.org/licenses/>.
 *
 */
#ifndef  MURSAT_c1101lib_h_INCLUDED__
#define MURSAT_c1101lib_h_INCLUDED__

#define C1101_FIFO_MAX_LEN 64

//read/write config registers:
#define SPIC1101_ADDR_IOCFG2    0x00
#define SPIC1101_ADDR_IOCFG1    0x01
#define SPIC1101_ADDR_IOCFG0    0x02
#define SPIC1101_ADDR_FIFOTHR   0x03
#define SPIC1101_ADDR_SYNC1     0x04
#define SPIC1101_ADDR_SYNC0     0x05
#define SPIC1101_ADDR_PKTLEN    0x06
#define SPIC1101_ADDR_PKTCTRL1  0x07
#define SPIC1101_ADDR_PKTCTRL0  0x08
#define SPIC1101_ADDR_ADDR      0x09
#define SPIC1101_ADDR_CHANNR    0x0A
#define SPIC1101_ADDR_FSCTRL1   0x0B
#define SPIC1101_ADDR_FSCTRL0   0x0C
#define SPIC1101_ADDR_FREQ2     0x0D
#define SPIC1101_ADDR_FREQ1     0x0E
#define SPIC1101_ADDR_FREQ0     0x0F
#define SPIC1101_ADDR_MDMCFG4   0x10
#define SPIC1101_ADDR_MDMCFG3   0x11
#define SPIC1101_ADDR_MDMCFG2   0x12
#define SPIC1101_ADDR_MDMCFG1   0x13
#define SPIC1101_ADDR_MDMCFG0   0x14
#define SPIC1101_ADDR_DEVIATN   0x15
#define SPIC1101_ADDR_MCSM2     0x16
#define SPIC1101_ADDR_MCSM1     0x17
#define SPIC1101_ADDR_MCSM0     0x18
#define SPIC1101_ADDR_FOCCFG    0x19
#define SPIC1101_ADDR_BSCFG     0x1A
#define SPIC1101_ADDR_AGCCTRL2  0x1B
#define SPIC1101_ADDR_AGCCTRL1  0x1C
#define SPIC1101_ADDR_AGCCTRL0  0x1D
#define SPIC1101_ADDR_WOREVT1   0x1E
#define SPIC1101_ADDR_WOREVT0   0x1F
#define SPIC1101_ADDR_WORCTRL   0x20
#define SPIC1101_ADDR_FREND1    0x21
#define SPIC1101_ADDR_FREND0    0x22
#define SPIC1101_ADDR_FSCAL3    0x23
#define SPIC1101_ADDR_FSCAL2    0x24
#define SPIC1101_ADDR_FSCAL1    0x25
#define SPIC1101_ADDR_FSCAL0    0x26
#define SPIC1101_ADDR_RCCTRL1   0x27
#define SPIC1101_ADDR_RCCTRL0   0x28
#define SPIC1101_ADDR_FSTEST    0x29
#define SPIC1101_ADDR_PTEST     0x2A
#define SPIC1101_ADDR_AGCTEST   0x2B
#define SPIC1101_ADDR_TEST2     0x2C
#define SPIC1101_ADDR_TEST1     0x2D
#define SPIC1101_ADDR_TEST0     0x2E

//commands:
#define SPIC1101_ADDR_SRES      0x30
#define SPIC1101_ADDR_SFSTXON   0x31
#define SPIC1101_ADDR_SXOFF     0x32
#define SPIC1101_ADDR_SCAL      0x33
#define SPIC1101_ADDR_SRX       0x34
#define SPIC1101_ADDR_STX       0x35
#define SPIC1101_ADDR_SIDLE     0x36
#define SPIC1101_ADDR_SWOR      0x38
#define SPIC1101_ADDR_SPWD      0x39
#define SPIC1101_ADDR_SFRX      0x3A
#define SPIC1101_ADDR_SFTX      0x3B
#define SPIC1101_ADDR_SWORRST   0x3C
#define SPIC1101_ADDR_SNOP      0x3D

//readonly registers:
#define SPIC1101_ADDR_PARTNUM        (0x30 | 0xC0)
#define SPIC1101_ADDR_VERSION        (0x31 | 0xC0)
#define SPIC1101_ADDR_FREQUEST       (0x32 | 0xC0)
#define SPIC1101_ADDR_LQI            (0x33 | 0xC0)
#define SPIC1101_ADDR_RSSI           (0x34 | 0xC0)
#define SPIC1101_ADDR_MARCSTATE      (0x35 | 0xC0)
#define SPIC1101_ADDR_WORTIME1       (0x36 | 0xC0)
#define SPIC1101_ADDR_WORTIME0       (0x37 | 0xC0)
#define SPIC1101_ADDR_PKTSTATUS      (0x38 | 0xC0)
#define SPIC1101_ADDR_VCO_VC_DAC     (0x39 | 0xC0)
#define SPIC1101_ADDR_TXBYTES        (0x3A | 0xC0)
#define SPIC1101_ADDR_RXBYTES        (0x3B | 0xC0)
#define SPIC1101_ADDR_RCCTRL1_STATUS (0x3C | 0xC0)
#define SPIC1101_ADDR_RCCTRL0_STATUS (0x3D | 0xC0)

#define SPIC1101_ADDR_FIFO_READ (0x3F | 0x80)
#define SPIC1101_ADDR_FIFO_READ_BURST (0x3F | 0x80 | 0xC0)
#define SPIC1101_ADDR_FIFO_WRITE 0x3F
#define SPIC1101_ADDR_FIFO_WRITE_BURST (0x3F | 0x40)

#define SPIC1101_SB_CHIP_NOT_RDY(x) (x & 0b10000000)
#define SPIC1101_SB_IDLE(x) (x & 0b01110000) == 0
#define SPIC1101_SB_RXMODE(x) (x & 0b01110000) == 0b0010000
#define SPIC1101_SB_TXMODE(x) (x & 0b01110000) == 0b0100000
#define SPIC1101_SB_FSTXON(x) (x & 0b01110000) == 0b0110000
#define SPIC1101_SB_CALIBRATE(x) (x & 0b01110000) == 0b1000000
#define SPIC1101_SB_SETTLING(x) (x & 0b01110000) == 0b1010000
#define SPIC1101_SB_RXFIFO_OVERFLOW(x) (x & 0b01110000) == 0b1100000
#define SPIC1101_SB_TXFIFO_OVERFLOW(x) (x & 0b01110000) == 0b1110000
#define SPIC1101_SB_FIFO_BYTES_AVAILABLE(x) (x & 0b00001111)

int16_t spi_c1101_read_register(char address);
int16_t spi_c1101_write_register(char address, char byte);
int16_t spi_c1101_strobe_command(char address);

void c1101_init(void);
char c1101_getVersion(void);
char c1101_getPartNum(void);
void c1101_handleStatusByte(char sb);
char c1101_getStatus(void);
uint16_t c1101_measureTemp(void);
void spi_c1101_dump_registers_to_usb(void);
void c1101_setFrequency(uint32_t freq, uint8_t freq_offset, uint8_t if_freq);

void c1101_transmitData(char *buffer, unsigned int len);

//max returned: 64 bytes
int c1101_readRXFifo(char *buffer);

#endif