From 8e6d1498b057f2598ed06416ab6fad2bdd90ba9c Mon Sep 17 00:00:00 2001 From: Bernhard Tittelbach Date: Sat, 19 May 2012 00:32:42 +0000 Subject: experimental settings 437.5 mhz ax.25 compatible 9k6 gfsk git-svn-id: https://svn.spreadspace.org/mur.sat@429 7de4ea59-55d0-425e-a1af-a3118ea81d4c --- software/hhd70dongle/c1101lib.c | 51 ++++++++++++++++++++++++++++++++--------- 1 file changed, 40 insertions(+), 11 deletions(-) (limited to 'software/hhd70dongle/c1101lib.c') diff --git a/software/hhd70dongle/c1101lib.c b/software/hhd70dongle/c1101lib.c index 57804ca..3ccd86b 100644 --- a/software/hhd70dongle/c1101lib.c +++ b/software/hhd70dongle/c1101lib.c @@ -89,7 +89,7 @@ int16_t spi_c1101_write_register(char address, char byte) return -1; _delay_ms(2); if (spi_c1101_write_byte_ok_get_status(byte) < 0) - return -1; + return -1; spi_cs_disable(); return 1; } @@ -180,13 +180,42 @@ void c1101_init(void) //flush FIFOs spi_c1101_strobe_command(SPIC1101_ADDR_SFRX); spi_c1101_strobe_command(SPIC1101_ADDR_SFTX); - //dump current default values to usb + //dump pre-init default values to usb spi_c1101_dump_registers_to_usb(); //enable analog temperature sensor on GDO0 spi_c1101_write_register(SPIC1101_ADDR_IOCFG0, 0x80); + // FIFOTHR RX FIFO and TX FIFO Thresholds + spi_c1101_write_register(SPIC1101_ADDR_FIFOTHR, 0x47); + // PKTCTRL0 Packet Automation Control + spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL0, 0x05); + // FSCTRL1 Frequency Synthesizer Control + spi_c1101_write_register(SPIC1101_ADDR_FSCTRL1, 0x06); + // FREQn Frequency Control Words + spi_c1101_write_register(SPIC1101_ADDR_FREQ2, 0x10); + spi_c1101_write_register(SPIC1101_ADDR_FREQ1, 0xD3); + spi_c1101_write_register(SPIC1101_ADDR_FREQ0, 0xB1); + // MDMCFGn Modem Configuration + spi_c1101_write_register(SPIC1101_ADDR_MDMCFG4, 0xF8); + spi_c1101_write_register(SPIC1101_ADDR_MDMCFG3, 0x83); + spi_c1101_write_register(SPIC1101_ADDR_MDMCFG2, 0x13); + spi_c1101_write_register(SPIC1101_ADDR_MDMCFG1, 0x00); + // DEVIATN Modem Deviation Setting + spi_c1101_write_register(SPIC1101_ADDR_DEVIATN, 0x07); + // MCSM0 Main Radio Control State Machine Configuration + spi_c1101_write_register(SPIC1101_ADDR_MCSM0, 0x18); + // FOCCFG Frequency Offset Compensation Configuration + spi_c1101_write_register(SPIC1101_ADDR_FOCCFG, 0x16); + // WORCTRL Wake On Radio Control + spi_c1101_write_register(SPIC1101_ADDR_WORCTRL, 0xFB); + // FSCALn Frequency Synthesizer Calibration + spi_c1101_write_register(SPIC1101_ADDR_FSCAL3, 0xE9); + spi_c1101_write_register(SPIC1101_ADDR_FSCAL2, 0x2A); + spi_c1101_write_register(SPIC1101_ADDR_FSCAL1, 0x00); + spi_c1101_write_register(SPIC1101_ADDR_FSCAL0, 0x1F); + // note: for now: assume f_xosc to be 26 Mhz // for ~433.125 Mhz -> freq = 1091741, freq_offset = 0 - c1101_setFrequency(1091741,0,15); + //c1101_setFrequency(1091741,0,15); } // freq: desired_carrier_freq [Hz] *2^16 / f_XOSC @@ -209,7 +238,7 @@ void c1101_setFrequency(uint32_t freq, uint8_t freq_offset, uint8_t if_freq) //set frequency offset spi_c1101_write_register(SPIC1101_ADDR_FSCTRL0, freq_offset); //spi_c1101_write_register(SPIC1101_ADDR_FSCTRL1, if_freq & 0x1F); - + //set channel 0 spi_c1101_write_register(SPIC1101_ADDR_CHANNR, 0); } @@ -256,7 +285,7 @@ char c1101_getStatus(void) { char sb=0; spi_cs_enable(); - spi_c1101_wait_chip_rdy(); + spi_c1101_wait_chip_rdy(); sb = spi_c1101_write_byte_ok_get_status(SPIC1101_ADDR_SNOP); spi_cs_disable(); //debug start @@ -275,8 +304,8 @@ void c1101_writeTXFifo(char *buffer, unsigned int len) { //check TXBYTES.NUM_TXBYTES // never write more bytes than avaiblabe or doom ensues - - + + } //max returned: 64 bytes @@ -284,10 +313,10 @@ int c1101_readRXFifo(char *buffer) { //check RXBYTES.NUM_RXBYTES // never read more bytes than avaiblabe or we will read garbage - - //note: if RX transmission fills fifo buffer at exact same time as last RX Fifo Bit is read via SPI, Fifo Pointer will not be properly updated + + //note: if RX transmission fills fifo buffer at exact same time as last RX Fifo Bit is read via SPI, Fifo Pointer will not be properly updated // and last read byte will be duplicated. // thus: don't last avialable FIFO Bytes unless we can be sure that it will be the last byte of a packet and we can be sure that a following duplicated byte is actually an Fifo duplication and not an actually recieved byte ! - + return 0; -} \ No newline at end of file +} -- cgit v1.2.3