From f4528d9b8397ffa6c15d5dbc67541948dd688e4f Mon Sep 17 00:00:00 2001 From: Christian Pointner Date: Fri, 13 Feb 2015 14:44:27 +0100 Subject: moved rda1846 code to lib --- software/avr.lib/rda1846.c | 485 +++++++++++++++++++++++++++++++++++++ software/avr.lib/rda1846.h | 67 +++++ software/avr.lib/rda1846_defines.h | 248 +++++++++++++++++++ 3 files changed, 800 insertions(+) create mode 100644 software/avr.lib/rda1846.c create mode 100644 software/avr.lib/rda1846.h create mode 100644 software/avr.lib/rda1846_defines.h (limited to 'software/avr.lib') diff --git a/software/avr.lib/rda1846.c b/software/avr.lib/rda1846.c new file mode 100644 index 0000000..43e66ff --- /dev/null +++ b/software/avr.lib/rda1846.c @@ -0,0 +1,485 @@ +/* + * spreadspace avr utils + * + * + * Copyright (C) 2013-2014 Christian Pointner + * + * This file is part of spreadspace avr utils. + * + * spreadspace avr utils is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * spreadspace avr utils is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with spreadspace avr utils. If not, see . + */ + +#include "LUFA/Drivers/Peripheral/TWI.h" +#include + +#include "rda1846.h" +#include "rda1846_defines.h" + +static uint8_t rda1846_write_register_raw(const uint8_t addr, const uint16_t data) +{ + if(TWI_StartTransmission(RDA1846_CHIP_ADDR | TWI_ADDRESS_WRITE,10) != TWI_ERROR_NoError) + return 1; + + if(!TWI_SendByte(addr | RDA1846_ADDR_W)) + goto i2c_error; + if(!TWI_SendByte((uint8_t)(data>>8))) + goto i2c_error; + if(!TWI_SendByte((uint8_t)data)) + goto i2c_error; + + TWI_StopTransmission(); + return 0; + +i2c_error: + TWI_StopTransmission(); + printf("I2C error (write_register_raw)\r\n"); + return 1; +} + +static uint8_t rda1846_read_register_raw(const uint8_t addr, uint16_t* data) +{ + if(TWI_StartTransmission(RDA1846_CHIP_ADDR | TWI_ADDRESS_WRITE,10) != TWI_ERROR_NoError) + return 1; + if(!TWI_SendByte(addr | RDA1846_ADDR_R)) + goto i2c_error; + + if(TWI_StartTransmission(RDA1846_CHIP_ADDR | TWI_ADDRESS_READ,10) != TWI_ERROR_NoError) + goto i2c_error; + uint8_t tmp; + if(!TWI_ReceiveByte(&tmp, 0)) + goto i2c_error; + *data = tmp << 8; + if(!TWI_ReceiveByte(&tmp, 1)) + goto i2c_error; + *data |= tmp; + + TWI_StopTransmission(); + return 0; + +i2c_error: + TWI_StopTransmission(); + printf("I2C error (read_register_raw)\r\n"); + return 1; +} + +static uint8_t rda1846_write_register(const uint8_t addr, const uint16_t data) +{ + if(addr < RDA1846_ADDR_LIMIT) + return rda1846_write_register_raw(addr, data); + + if(addr > RDA1846_ADDR_LIMIT) { + uint8_t ret = rda1846_write_register_raw(RDA1846_ADDR_LIMIT, 1); + if(ret) return ret; + + ret = rda1846_write_register_raw(addr, data); + if(ret) return ret; + + return rda1846_write_register_raw(RDA1846_ADDR_LIMIT, 0); + } + return 1; +} + +static uint8_t rda1846_read_register(const uint8_t addr, uint16_t* data) +{ + if(addr < RDA1846_ADDR_LIMIT) + return rda1846_read_register_raw(addr, data); + + if(addr > RDA1846_ADDR_LIMIT) { + uint8_t ret = rda1846_write_register_raw(RDA1846_ADDR_LIMIT, 1); + if(ret) return ret; + + ret = rda1846_read_register_raw(addr - RDA1846_ADDR_LIMIT + 1, data); + if(ret) return ret; + + return rda1846_write_register_raw(RDA1846_ADDR_LIMIT, 0); + } + return 1; +} + +static rf_band_t rf_band_; +static channel_bw_t channel_bw_; +static rda1846_state_t state_; + +/* + * EXTERNAL INTERFACE + */ + +char* rda1846_rf_band_to_string(rf_band_t b) +{ + switch(b) + { + case b_2m: return "2m (134-174 MHz)"; + case b_1m5: return "1.5m (200-260 MHz)"; + case b_70cm: return "70cm (400-520 MHz)"; + } + return ""; +} + +char* rda1846_channel_bw_to_string(channel_bw_t bw) +{ + switch(bw) + { + case bw_12k5: return "12,5 kHz"; + case bw_25k: return "25 kHz"; + } + return ""; +} + +char* rda1846_state_to_string(rda1846_state_t s) +{ + switch(s) + { + case powerdown: return "powerdown"; + case idle: return "idle"; + case receive: return "receiving"; + case transmit: return "transmitting"; + } + return ""; +} + +void rda1846_init(void) +{ + TWI_Init(TWI_BIT_PRESCALE_1, TWI_BITLENGTH_FROM_FREQ(1, 200000)); +} + +void rda1846_reg_init(void) +{ + rda1846_write_register(RDA1846_REG_CTL, RDA1846_CTL_SOFT_RST); + rda1846_write_register(RDA1846_REG_CTL, RDA1846_CTL_PDN); + + rda1846_write_register(RDA1846_REG_XTAL, RDA1846_XTAL_FREQ); + rda1846_write_register(RDA1846_REG_ADCLK, RDA1846_ADCLK_FREQ); + rda1846_write_register(RDA1846_REG_CLK_MODE, RDA1846_CLK_MODE); + + rda1846_write_register(RDA1846_REG_RF_BAND, RDA1846_RF_BAND_2M); + rf_band_ = b_2m; + + rda1846_write_register(RDA1846_REG_CTL, RDA1846_CTL_CH_12K5 | RDA1846_CTL_RX_M_TX_M | RDA1846_CTL_PDN); + channel_bw_ = bw_12k5; + state_ = idle; + + rda1846_write_register(RDA1846_REG_TX_VOICE, RDA1846_TX_VOICE_NONE); +// rda1846_write_register(RDA1846_REG_TX_VOICE, RDA1846_TX_VOICE_MIC); +// rda1846_write_register(RDA1846_REG_TX_VOICE, RDA1846_TX_VOICE_TONE2); +// rda1846_write_register(RDA1846_REG_DTMF_T2, 6689); + + rda1846_write_register(RDA1846_REG_DTMF_C01, (RDA1846_DTMF_C0 << 8) | RDA1846_DTMF_C1); + rda1846_write_register(RDA1846_REG_DTMF_C23, (RDA1846_DTMF_C1 << 8) | RDA1846_DTMF_C3); + rda1846_write_register(RDA1846_REG_DTMF_C45, (RDA1846_DTMF_C3 << 8) | RDA1846_DTMF_C5); + rda1846_write_register(RDA1846_REG_DTMF_C67, (RDA1846_DTMF_C6 << 8) | RDA1846_DTMF_C7); + rda1846_write_register(RDA1846_REG_DTMF_CTL, RDA1846_DTMF_DUAL | RDA1846_DTMF_EN); + rda1846_write_register(RDA1846_REG_INT, RDA1846_INT_DTMF_IDLE); + + rda1846_gpio_default(); +} + +void rda1846_soft_reset(void) +{ + rda1846_write_register(RDA1846_REG_CTL, RDA1846_CTL_SOFT_RST); +} + + + +void rda1846_set_band(rf_band_t b) +{ + uint16_t data = RDA1846_RF_BAND_2M; + if(b == b_1m5) data = RDA1846_RF_BAND_1M5; + if(b == b_70cm) data = RDA1846_RF_BAND_70CM; + if(!rda1846_write_register(RDA1846_REG_RF_BAND, data)) + rf_band_ = b; +} + +rf_band_t rda1846_get_band(void) +{ + return rf_band_; +} + +void rda1846_set_bw(channel_bw_t bw) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_CTL, &data)) + return; + + data &= RDA1846_CTL_CH_RESET; + data |= bw == bw_12k5 ? RDA1846_CTL_CH_12K5 : RDA1846_CTL_CH_25K; + if(!rda1846_write_register(RDA1846_REG_CTL, data)) + channel_bw_ = bw; +} + +channel_bw_t rda1846_get_bw(void) +{ + return channel_bw_; +} + +uint8_t rda1846_set_freq_kHz(int32_t freq) +{ + if((rf_band_ == b_2m && (freq < RDA1846_BAND_2M_LOW || freq > RDA1846_BAND_2M_HIGH)) || + (rf_band_ == b_1m5 && (freq < RDA1846_BAND_1M5_LOW || freq > RDA1846_BAND_1M5_HIGH)) || + (rf_band_ == b_70cm && (freq < RDA1846_BAND_70CM_LOW || freq > RDA1846_BAND_70CM_HIGH)) ) + return 1; + + freq = freq<<3; + uint8_t ret = rda1846_write_register(RDA1846_REG_FREQH, ((freq>>16) & 0x00003FFF)); + if(ret) + return 1; + + return rda1846_write_register(RDA1846_REG_FREQL, (freq & 0x0000FFFF)); +} + +static int32_t corr_freq(int32_t f) +{ + float corr = RDA1846_FREQ_CORR_2M; + if(rf_band_ == b_1m5) corr = RDA1846_FREQ_CORR_1M5; + if(rf_band_ == b_70cm) corr = RDA1846_FREQ_CORR_70CM; + return (int32_t)(((float)f)/corr); +} + +int32_t rda1846_get_freq_kHz(void) +{ + if(state_ == powerdown || state_ == idle) + return -1; + + uint16_t data; + uint8_t ret = rda1846_read_register(RDA1846_REG_FREQH, &data); + if(ret) + return -1; + + int32_t freq = (((uint32_t)(data & 0x3FFF))<<16); + ret = rda1846_read_register(RDA1846_REG_FREQL, &data); + if(ret) + return -1; + + freq = corr_freq((freq+data)>>3); + return (freq / 8) + ((freq % 8) < 4 ? 0 : 1); +} + + + +void rda1846_powerdown(void) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_CTL, &data)) + return; + + data &= ~(RDA1846_CTL_TX | RDA1846_CTL_RX | RDA1846_CTL_CHIP_CAL | RDA1846_CTL_PDN); + if(!rda1846_write_register(RDA1846_REG_CTL, data)) + state_ = powerdown; +} + +void rda1846_idle(void) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_CTL, &data)) + return; + + data &= ~(RDA1846_CTL_TX | RDA1846_CTL_RX | RDA1846_CTL_CHIP_CAL); + data |= RDA1846_CTL_PDN; + if(!rda1846_write_register(RDA1846_REG_CTL, data)) + state_ = idle; +} + +void rda1846_receive(void) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_CTL, &data)) + return; + + data &= ~(RDA1846_CTL_TX); + data |= RDA1846_CTL_RX | RDA1846_CTL_CHIP_CAL | RDA1846_CTL_PDN; + if(!rda1846_write_register(RDA1846_REG_CTL, data)) + state_ = receive; +} + +void rda1846_transmit(void) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_CTL, &data)) + return; + + data &= ~(RDA1846_CTL_RX); + data |= RDA1846_CTL_TX | RDA1846_CTL_CHIP_CAL | RDA1846_CTL_PDN; + if(!rda1846_write_register(RDA1846_REG_CTL, data)) + state_ = transmit; +} + +rda1846_state_t rda1846_get_state(void) +{ + return state_; +} + + + +uint16_t rda1846_get_dtmf(uint8_t* idx1, uint8_t* idx2, uint8_t* code, uint8_t* valid) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_DTMF_OUT, &data)) + return 0xFFFF; + + if(idx1) *idx1 = (uint8_t)((data & 0x0700)>>8); + if(idx2) *idx2 = (uint8_t)((data & 0x00E0)>>5); + if(code) *code = (uint8_t)(data & 0x000F); + if(valid) *valid = data & 0x0010 ? 0 : 1; + + return data; +} + +void rda1846_clear_int(void) +{ + rda1846_write_register(0x00, 0x1846); +} + + + +void rda1846_set_volume(int8_t vol) +{ + uint16_t data; + if(vol < -30 || vol > 0) + return; + + if(vol >= -15) + data = 0x000F | (((vol + 15)<<4) & 0xF0); + else + data = (vol + 30) & 0x0F; + + rda1846_write_register(RDA1846_REG_RX_VOICE, data); +} + +int8_t rda1846_get_volume(void) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_RX_VOICE, &data)) + return 1; + + return (int8_t)(((data & 0x00F0)>>4) + (data & 0x000F)) - 30; +} + + + +void rda1846_gpio_default(void) +{ + rda1846_write_register(RDA1846_REG_GPIO, RDA1846_GPIO_7_VOX | RDA1846_GPIO_6_SQ | + RDA1846_GPIO_5_TXON_RF | RDA1846_GPIO_4_RXON_RF | + RDA1846_GPIO_2_INT); +} + +void rda1846_gpio_AA(void) +{ + rda1846_write_register(RDA1846_REG_GPIO, RDA1846_GPIO_7_HIGH | RDA1846_GPIO_6_LOW | + RDA1846_GPIO_5_HIGH | RDA1846_GPIO_4_LOW | + RDA1846_GPIO_3_HIGH | RDA1846_GPIO_2_LOW | + RDA1846_GPIO_1_HIGH | RDA1846_GPIO_0_LOW); +} + +void rda1846_gpio_55(void) +{ + rda1846_write_register(RDA1846_REG_GPIO, RDA1846_GPIO_7_LOW | RDA1846_GPIO_6_HIGH | + RDA1846_GPIO_5_LOW | RDA1846_GPIO_4_HIGH | + RDA1846_GPIO_3_LOW | RDA1846_GPIO_2_HIGH | + RDA1846_GPIO_1_LOW | RDA1846_GPIO_0_HIGH); +} + +void rda1846_gpio_off(void) +{ + rda1846_write_register(RDA1846_REG_GPIO, RDA1846_GPIO_7_HI_Z | RDA1846_GPIO_6_HI_Z | + RDA1846_GPIO_5_HI_Z | RDA1846_GPIO_4_HI_Z | + RDA1846_GPIO_3_HI_Z | RDA1846_GPIO_2_HI_Z | + RDA1846_GPIO_1_HI_Z | RDA1846_GPIO_0_HI_Z); +} + + + +int16_t rda1846_get_rssi(void) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_RSSI, &data)) + return -1; + + return ((int16_t)(data & 0x03FF) - 135*8); +} + +int16_t rda1846_get_vssi(void) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_VSSI, &data)) + return -1; + + return (int16_t)data; +} + +uint16_t rda1846_get_flags(void) +{ + uint16_t data; + if(rda1846_read_register(RDA1846_REG_FLAG, &data)) + return 0xFFFF; + + return data & RDA1846_FLAGS_MASK; +} + + + +static char* rda1846_regaddr_to_string(uint8_t addr) +{ + switch(addr) { + case RDA1846_REG_CTL: return "CTL"; + case RDA1846_REG_GPIO: return "GPIO"; + case RDA1846_REG_INT: return "INT"; + case RDA1846_REG_FLAG: return "FLAG"; + case RDA1846_REG_RSSI: return "RSSI"; + case RDA1846_REG_VSSI: return "VSSI"; + case RDA1846_REG_CLK_MODE: return "CLK_MODE"; + case RDA1846_REG_XTAL: return "XTAL"; + case RDA1846_REG_ADCLK: return "ADCLK"; + case RDA1846_REG_RF_BAND: return "RF_BAND"; + case RDA1846_REG_FREQH: return "FREQH"; + case RDA1846_REG_FREQL: return "FREQL"; + case RDA1846_REG_PA_BIAS: return "PA_BIAS"; + case RDA1846_REG_TX_VOICE: return "TX_VOICE"; + case RDA1846_REG_VOX_OPEN: return "VOX_OPEN"; + case RDA1846_REG_VOX_SHUT: return "VOX_SHUT"; + case RDA1846_REG_SUBAUDIO: return "SUBAUDIO"; + case RDA1846_REG_RX_VOICE: return "RX_VOICE"; + case RDA1846_REG_SQ_OPEN: return "SQ_OPEN"; + case RDA1846_REG_SQ_SHUT: return "SQ_SHUT"; + case RDA1846_REG_DTMF_CTL: return "DTMF_CTL"; + case RDA1846_REG_DTMF_T1: return "DTMF_T1"; + case RDA1846_REG_DTMF_T2: return "DTMF_T2"; + case RDA1846_REG_DTMF_C01: return "DTMF_C01"; + case RDA1846_REG_DTMF_C23: return "DTMF_C23"; + case RDA1846_REG_DTMF_C45: return "DTMF_C45"; + case RDA1846_REG_DTMF_C67: return "DTMF_C67"; + case RDA1846_REG_DTMF_OUT: return "DTMF_OUT"; + default: return "unknown"; + } +} + +void rda1846_dump_register(void) +{ + printf("RDA1846: register dump\r\n"); + + const uint8_t regs[] = { RDA1846_REG_CLK_MODE, RDA1846_REG_XTAL, RDA1846_REG_ADCLK, + RDA1846_REG_RF_BAND, RDA1846_REG_FREQH, RDA1846_REG_FREQL, + RDA1846_REG_CTL, RDA1846_REG_INT, RDA1846_REG_GPIO, + RDA1846_REG_PA_BIAS, RDA1846_REG_TX_VOICE, RDA1846_REG_VOX_OPEN, RDA1846_REG_VOX_SHUT, + RDA1846_REG_SUBAUDIO, RDA1846_REG_RX_VOICE, RDA1846_REG_SQ_OPEN, RDA1846_REG_SQ_SHUT, + RDA1846_REG_DTMF_CTL, RDA1846_REG_DTMF_OUT, RDA1846_REG_DTMF_T1, RDA1846_REG_DTMF_T2, + RDA1846_REG_RSSI, RDA1846_REG_VSSI, RDA1846_REG_FLAG }; + + int i; + for(i=0; i + * + * This file is part of spreadspace avr utils. + * + * spreadspace avr utils is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * spreadspace avr utils is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with spreadspace avr utils. If not, see . + */ + +#ifndef SPREADAVR_rda1846_h_INCLUDED +#define SPREADAVR_rda1846_h_INCLUDED + +typedef enum { b_2m, b_1m5, b_70cm } rf_band_t; +char* rda1846_rf_band_to_string(rf_band_t); +typedef enum { bw_12k5, bw_25k } channel_bw_t; +char* rda1846_channel_bw_to_string(channel_bw_t); +typedef enum { powerdown, idle, receive, transmit } rda1846_state_t; +char* rda1846_state_to_string(rda1846_state_t); + +void rda1846_init(void); +void rda1846_reg_init(void); +void rda1846_soft_reset(void); + +void rda1846_powerdown(void); +void rda1846_idle(void); +void rda1846_receive(void); +void rda1846_transmit(void); +rda1846_state_t rda1846_get_state(void); + +void rda1846_set_band(rf_band_t); +rf_band_t rda1846_get_band(void); +void rda1846_set_bw(channel_bw_t); +channel_bw_t rda1846_get_bw(void); +uint8_t rda1846_set_freq_kHz(int32_t freq); +int32_t rda1846_get_freq_kHz(void); + +uint16_t rda1846_get_dtmf(uint8_t*, uint8_t*, uint8_t*, uint8_t*); +void rda1846_clear_int(void); + +void rda1846_set_volume(int8_t); +int8_t rda1846_get_volume(void); + +void rda1846_gpio_default(void); +void rda1846_gpio_55(void); +void rda1846_gpio_AA(void); +void rda1846_gpio_off(void); + +int16_t rda1846_get_rssi(void); +int16_t rda1846_get_vssi(void); +uint16_t rda1846_get_flags(void); + +void rda1846_dump_register(void); + +#endif diff --git a/software/avr.lib/rda1846_defines.h b/software/avr.lib/rda1846_defines.h new file mode 100644 index 0000000..968475e --- /dev/null +++ b/software/avr.lib/rda1846_defines.h @@ -0,0 +1,248 @@ +/* + * + * mur.sat + * + * Somewhen in the year 20xx, mur.at will have a nano satellite launched + * into a low earth orbit (310 km above the surface of our planet). The + * satellite itself is a TubeSat personal satellite kit, developed and + * launched by interorbital systems. mur.sat is a joint venture of mur.at, + * ESC im Labor and realraum. + * + * Please visit the project hompage at sat.mur.at for further information. + * + * + * Copyright (C) 2013-2015 Christian Pointner + * + * This file is part of mur.sat. + * + * mur.sat is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * mur.sat is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with mur.sat. If not, see . + * + */ + +#ifndef MURSAT_rda1846_defines_h_INCLUDED +#define MURSAT_rda1846_defines_h_INCLUDED + +// TWI +#define RDA1846_CHIP_ADDR 0xE2 +#define RDA1846_ADDR_W (0<<7) +#define RDA1846_ADDR_R (1<<7) +#define RDA1846_ADDR_LIMIT 0x7F + + +// registers +#define RDA1846_REG_CTL 0x30 +#define RDA1846_REG_GPIO 0x1F +#define RDA1846_REG_INT 0x2D +#define RDA1846_REG_FLAG 0x5C +#define RDA1846_REG_RSSI 0x5F +#define RDA1846_REG_VSSI 0x60 + +#define RDA1846_REG_CLK_MODE 0x04 +#define RDA1846_REG_XTAL 0x2B +#define RDA1846_REG_ADCLK 0x2C + +#define RDA1846_REG_RF_BAND 0x0F +#define RDA1846_REG_FREQH 0x29 +#define RDA1846_REG_FREQL 0x2A + +#define RDA1846_REG_PA_BIAS 0x0A +#define RDA1846_REG_TX_VOICE 0x3C +#define RDA1846_REG_VOX_OPEN 0x41 +#define RDA1846_REG_VOX_SHUT 0x42 + +#define RDA1846_REG_RX_VOICE 0x44 +#define RDA1846_REG_SUBAUDIO 0x45 +#define RDA1846_REG_SQ_OPEN 0x48 +#define RDA1846_REG_SQ_SHUT 0x49 + +#define RDA1846_REG_DTMF_CTL 0x63 +#define RDA1846_REG_DTMF_T1 0x35 +#define RDA1846_REG_DTMF_T2 0x36 +#define RDA1846_REG_DTMF_C01 0x66 +#define RDA1846_REG_DTMF_C23 0x67 +#define RDA1846_REG_DTMF_C45 0x68 +#define RDA1846_REG_DTMF_C67 0x69 +#define RDA1846_REG_DTMF_OUT 0x6C + +//freq +#ifdef RDA_QUARTZ_12M288 +#define RDA1846_FREQ_CORR_2M 73.1428567759 +#endif // RDA_QUARTZ_12M288 +#ifdef RDA_QUARTZ_13M +#define RDA1846_FREQ_CORR_2M 69.136878448 +#endif // RDA_QUARTZ_13M + +#define RDA1846_FREQ_CORR_1M5 RDA1846_FREQ_CORR_2M/1.5 +#define RDA1846_FREQ_CORR_70CM RDA1846_FREQ_CORR_2M/3.0 + + +// init values +#define RDA1846_RF_BAND_2M 0x00E4 // select 2m Band +#define RDA1846_BAND_2M_LOW 134000 // kHz +#define RDA1846_BAND_2M_HIGH 174000 // kHZ + +#define RDA1846_RF_BAND_1M5 0x00A4 // select 1.5m Band +#define RDA1846_BAND_1M5_LOW 200000 // kHz +#define RDA1846_BAND_1M5_HIGH 260000 // kHZ + +#define RDA1846_RF_BAND_70CM 0x0024 // select 70cm Band +#define RDA1846_BAND_70CM_LOW 400000 // kHz +#define RDA1846_BAND_70CM_HIGH 520000 // kHZ + +#ifdef RDA_QUARTZ_12M288 +#define RDA1846_XTAL_FREQ 12288 // 12.288 MHz +#define RDA1846_ADCLK_FREQ 6144 // 12.288/2 MHz +#define RDA1846_CLK_MODE 0x0F11 // 12-14 MHz +#endif // RDA_QUARTZ_12M288 + +#ifdef RDA_QUARTZ_13M +#define RDA1846_XTAL_FREQ 13000 // 13.000 MHz +#define RDA1846_ADCLK_FREQ 6500 // 13.000/2 MHz +#define RDA1846_CLK_MODE 0x0F11 // 12-14 MHz +#endif // RDA_QUARTZ_13M + + + + +// ctl +#define RDA1846_CTL_CH_25K 0x3000 +#define RDA1846_CTL_CH_12K5 0x0000 +#define RDA1846_CTL_CH_RESET 0xCFFF + +#define RDA1846_CTL_TAIL_ELIM 0x0800 + +#define RDA1846_CTL_RX_A_TX_A 0x0200 +#define RDA1846_CTL_RX_A_TX_M 0x0100 +#define RDA1846_CTL_RX_M_TX_M 0x0000 + +#define RDA1846_CTL_MUTE 0x0080 +#define RDA1846_CTL_TX 0x0040 +#define RDA1846_CTL_RX 0x0020 +#define RDA1846_CTL_VOX 0x0010 +#define RDA1846_CTL_SQ 0x0008 +#define RDA1846_CTL_PDN 0x0004 +#define RDA1846_CTL_CHIP_CAL 0x0002 +#define RDA1846_CTL_SOFT_RST 0x0001 + + +// flag +#define RDA1846_FLAG_DTMF_IDLE 0x1000 +#define RDA1846_FLAG_RXON_RF 0x0400 +#define RDA1846_FLAG_TXON_RF 0x0200 +#define RDA1846_FLAG_INVERT_DET 0x0080 +#define RDA1846_FLAG_CSS_CMP 0x0004 +#define RDA1846_FLAG_SQ 0x0002 +#define RDA1846_FLAG_VOX 0x0001 + +#define RDA1846_FLAGS_MASK 0x1687 + + +// gpio +#define RDA1846_GPIO_7_HI_Z 0x0000 +#define RDA1846_GPIO_7_VOX 0x4000 +#define RDA1846_GPIO_7_LOW 0x8000 +#define RDA1846_GPIO_7_HIGH 0xC000 + +#define RDA1846_GPIO_6_HI_Z 0x0000 +#define RDA1846_GPIO_6_SQ 0x1000 +#define RDA1846_GPIO_6_LOW 0x2000 +#define RDA1846_GPIO_6_HIGH 0x3000 + +#define RDA1846_GPIO_5_HI_Z 0x0000 +#define RDA1846_GPIO_5_TXON_RF 0x0400 +#define RDA1846_GPIO_5_LOW 0x0800 +#define RDA1846_GPIO_5_HIGH 0x0C00 + +#define RDA1846_GPIO_4_HI_Z 0x0000 +#define RDA1846_GPIO_4_RXON_RF 0x0100 +#define RDA1846_GPIO_4_LOW 0x0200 +#define RDA1846_GPIO_4_HIGH 0x0300 + +#define RDA1846_GPIO_3_HI_Z 0x0000 +#define RDA1846_GPIO_3_SDO 0x0040 +#define RDA1846_GPIO_3_LOW 0x0080 +#define RDA1846_GPIO_3_HIGH 0x00C0 + +#define RDA1846_GPIO_2_HI_Z 0x0000 +#define RDA1846_GPIO_2_INT 0x0010 +#define RDA1846_GPIO_2_LOW 0x0020 +#define RDA1846_GPIO_2_HIGH 0x0030 + +#define RDA1846_GPIO_1_HI_Z 0x0000 +#define RDA1846_GPIO_1_CODE 0x0004 +#define RDA1846_GPIO_1_LOW 0x0008 +#define RDA1846_GPIO_1_HIGH 0x000C + +#define RDA1846_GPIO_0_HI_Z 0x0000 +#define RDA1846_GPIO_0_CSS 0x0001 +#define RDA1846_GPIO_0_LOW 0x0002 +#define RDA1846_GPIO_0_HIGH 0x0003 + + +// int +#define RDA1846_INT_CSS_CMP 0x0200 +#define RDA1846_INT_RXON_RF 0x0100 +#define RDA1846_INT_TXON_RF 0x0080 +#define RDA1846_INT_DTMF_IDLE 0x0040 +#define RDA1846_INT_INVERT_DET 0x0020 +#define RDA1846_INT_IDLE_TO 0x0010 +#define RDA1846_INT_RXON_RF_TO 0x0008 +#define RDA1846_INT_SQ 0x0004 +#define RDA1846_INT_TXON_RF_TO 0x0002 +#define RDA1846_INT_VOX 0x0001 + + +// tx voice channel +#define RDA1846_TX_VOICE_MIC 0x0958 +#define RDA1846_TX_VOICE_TONE2 0x4958 +#define RDA1846_TX_VOICE_GPIO1 0x8958 +#define RDA1846_TX_VOICE_NONE 0xC958 + + +// DTMF ctl +#define RDA1846_DTMF_SINGLE 0x0200 +#define RDA1846_DTMF_DUAL 0x0000 +#define RDA1846_DTMF_EN 0x0100 + +// DTMF tone freq +#include + +#define dtmf_tone_freq_hz(value) (uint16_t)round(value/4.096) +#define dtmf_tone_freq_value(hz) (uint16_t)round(hz*4.096) + +#ifdef RDA_QUARTZ_12M288 +// DTMF frequencies @ 12.288 MHz - these are the defaults... are they? +#define RDA1846_DTMF_C0 0x61 // 697 Hz +#define RDA1846_DTMF_C1 0x5B // 770 Hz +#define RDA1846_DTMF_C2 0x53 // 852 Hz +#define RDA1846_DTMF_C3 0x4B // 941 Hz +#define RDA1846_DTMF_C4 0x2C // 1209 Hz +#define RDA1846_DTMF_C5 0x1E // 1336 Hz +#define RDA1846_DTMF_C6 0x0A // 1477 Hz +#define RDA1846_DTMF_C7 0xF6 // 1633 Hz +#endif // RDA_QUARTZ_12M8 + +#ifdef RDA_QUARTZ_13M +// DTMF frequencies @ 13 MHz - these are the defaults... +#define RDA1846_DTMF_C0 0x61 // 697 Hz +#define RDA1846_DTMF_C1 0x5E // 770 Hz +#define RDA1846_DTMF_C2 0x57 // 852 Hz +#define RDA1846_DTMF_C3 0x4B // 941 Hz +#define RDA1846_DTMF_C4 0x31 // 1209 Hz +#define RDA1846_DTMF_C5 0x1E // 1336 Hz +#define RDA1846_DTMF_C6 0x0F // 1477 Hz +#define RDA1846_DTMF_C7 0xFB // 1633 Hz +#endif // RDA_QUARTZ_13M + +#endif -- cgit v1.2.3