From d130078d79dcd8831d660336fc9d9404bc97bb85 Mon Sep 17 00:00:00 2001 From: Christian Pointner Date: Mon, 23 Feb 2015 21:05:24 +0100 Subject: hhd70: implemented also register writes reads and writes to registers are now normalized --- software/avr.lib/cc1101.c | 302 +++++++++++++++++++++++++------------- software/avr.lib/cc1101.h | 15 +- software/avr.lib/cc1101_defines.h | 64 ++++++++ 3 files changed, 271 insertions(+), 110 deletions(-) diff --git a/software/avr.lib/cc1101.c b/software/avr.lib/cc1101.c index 8bace9d..96473b0 100644 --- a/software/avr.lib/cc1101.c +++ b/software/avr.lib/cc1101.c @@ -213,373 +213,479 @@ static cc1101_state_t cc1101_marcstate_to_state(uint8_t marcstate) cc1101_state_t cc1101_get_state(void) { - return cc1101_marcstate_to_state(cc1101_spi_read_register(CC1101_REG_RO_MARCSTATE)); + return cc1101_marcstate_to_state(cc1101_get_marcstate()); } + + + + +uint32_t cc1101_get_freq_hz(void) +{ + return (uint32_t)((float)(cc1101_get_freq()) * drv.freq_corr); +} + +void cc1101_set_freq_hz(uint32_t hz) +{ + uint32_t freq = (uint32_t)((float)hz / drv.freq_corr); + if(freq <= 0x3FFFFF) + + // TODO: this is only allowed in idle mode + cc1101_spi_write_register(CC1101_REG_RW_FREQ0, freq & 0xFF); + cc1101_spi_write_register(CC1101_REG_RW_FREQ1, (freq >> 8) & 0xFF); + cc1101_spi_write_register(CC1101_REG_RW_FREQ2, (freq >> 16) & 0x3F); +} + + + +// normalized register access + uint8_t cc1101_get_iocfg0(void) { - return cc1101_spi_read_register(CC1101_REG_RW_IOCFG0) & 0x7F; + return cc1101_spi_read_register(CC1101_REG_RW_IOCFG0) & CC1101_REG_RW_IOCFG0_MASK; } void cc1101_set_iocfg0(uint8_t iocfg) { + cc1101_spi_write_register(CC1101_REG_RW_IOCFG0, iocfg & CC1101_REG_RW_IOCFG0_MASK); } uint8_t cc1101_get_iocfg1(void) { - return cc1101_spi_read_register(CC1101_REG_RW_IOCFG1); + return cc1101_spi_read_register(CC1101_REG_RW_IOCFG1) & CC1101_REG_RW_IOCFG1_MASK; } void cc1101_set_iocfg1(uint8_t iocfg) { + cc1101_spi_write_register(CC1101_REG_RW_IOCFG1, iocfg & CC1101_REG_RW_IOCFG1_MASK); } uint8_t cc1101_get_iocfg2(void) { - return cc1101_spi_read_register(CC1101_REG_RW_IOCFG2); + return cc1101_spi_read_register(CC1101_REG_RW_IOCFG2) & CC1101_REG_RW_IOCFG2_MASK; } void cc1101_set_iocfg2(uint8_t iocfg) { + cc1101_spi_write_register(CC1101_REG_RW_IOCFG2, iocfg & CC1101_REG_RW_IOCFG2_MASK); } uint8_t cc1101_get_fifothr(void) { - return cc1101_spi_read_register(CC1101_REG_RW_FIFOTHR) & 0x7F; + return cc1101_spi_read_register(CC1101_REG_RW_FIFOTHR) & CC1101_REG_RW_FIFOTHR_MASK; } void cc1101_set_fifothr(uint8_t fifothr) { + cc1101_spi_write_register(CC1101_REG_RW_FIFOTHR, fifothr & CC1101_REG_RW_FIFOTHR_MASK); } uint16_t cc1101_get_sync(void) { - uint16_t s = cc1101_spi_read_register(CC1101_REG_RW_SYNC1); - s = s << 8; - s |= cc1101_spi_read_register(CC1101_REG_RW_SYNC0); - return s; + uint16_t sync = cc1101_spi_read_register(CC1101_REG_RW_SYNC1) & CC1101_REG_RW_SYNC1_MASK; + sync = sync << 8; + sync |= cc1101_spi_read_register(CC1101_REG_RW_SYNC0) & CC1101_REG_RW_SYNC0_MASK; + return sync; } void cc1101_set_sync(uint16_t sync) { + cc1101_spi_write_register(CC1101_REG_RW_SYNC0, (uint8_t)(sync) & CC1101_REG_RW_SYNC0_MASK); + sync = sync >> 8; + cc1101_spi_write_register(CC1101_REG_RW_SYNC1, (uint8_t)(sync) & CC1101_REG_RW_SYNC1_MASK); } uint8_t cc1101_get_pktlen(void) { - return cc1101_spi_read_register(CC1101_REG_RW_PKTLEN); + return cc1101_spi_read_register(CC1101_REG_RW_PKTLEN) & CC1101_REG_RW_PKTLEN_MASK; } void cc1101_set_pktlen(uint8_t len) { + cc1101_spi_write_register(CC1101_REG_RW_PKTLEN, len & CC1101_REG_RW_PKTLEN_MASK); } uint16_t cc1101_get_pktctrl(void) { - uint16_t p = cc1101_spi_read_register(CC1101_REG_RW_PKTCTRL1) & 0xEF; - p = p << 8; - p |= cc1101_spi_read_register(CC1101_REG_RW_PKTCTRL0) & 0x77; - return p; + uint16_t ctrl = cc1101_spi_read_register(CC1101_REG_RW_PKTCTRL1) & CC1101_REG_RW_PKTCTRL1_MASK; + ctrl = ctrl << 8; + ctrl |= cc1101_spi_read_register(CC1101_REG_RW_PKTCTRL0) & CC1101_REG_RW_PKTCTRL0_MASK; + return ctrl; } void cc1101_set_pktctrl(uint16_t ctrl) { + cc1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, (uint8_t)(ctrl) & CC1101_REG_RW_PKTCTRL0_MASK); + ctrl = ctrl >> 8; + cc1101_spi_write_register(CC1101_REG_RW_PKTCTRL1, (uint8_t)(ctrl) & CC1101_REG_RW_PKTCTRL1_MASK); } uint8_t cc1101_get_addr(void) { - return cc1101_spi_read_register(CC1101_REG_RW_ADDR); + return cc1101_spi_read_register(CC1101_REG_RW_ADDR) & CC1101_REG_RW_ADDR_MASK; } void cc1101_set_addr(uint8_t addr) { + cc1101_spi_write_register(CC1101_REG_RW_ADDR, addr & CC1101_REG_RW_ADDR_MASK); } uint8_t cc1101_get_channr(void) { - return cc1101_spi_read_register(CC1101_REG_RW_CHANNR); + return cc1101_spi_read_register(CC1101_REG_RW_CHANNR) & CC1101_REG_RW_CHANNR_MASK; } void cc1101_set_channr(uint8_t nr) { + cc1101_spi_write_register(CC1101_REG_RW_CHANNR, nr & CC1101_REG_RW_CHANNR_MASK); } uint8_t cc1101_get_iffreq(void) { - return cc1101_spi_read_register(CC1101_REG_RW_FSCTRL1) & 0x1F; + return cc1101_spi_read_register(CC1101_REG_RW_FSCTRL1) & CC1101_REG_RW_FSCTRL1_MASK; } void cc1101_set_iffreq(uint8_t iffreq) { + cc1101_spi_write_register(CC1101_REG_RW_FSCTRL1, iffreq & CC1101_REG_RW_FSCTRL1_MASK); } uint8_t cc1101_get_freq_offset(void) { - return cc1101_spi_read_register(CC1101_REG_RW_FSCTRL0); + return cc1101_spi_read_register(CC1101_REG_RW_FSCTRL0) & CC1101_REG_RW_FSCTRL0_MASK; } void cc1101_set_freq_offset(uint8_t freqoff) { + cc1101_spi_write_register(CC1101_REG_RW_FSCTRL0, freqoff & CC1101_REG_RW_FSCTRL0_MASK); } uint32_t cc1101_get_freq(void) { - uint32_t f = cc1101_spi_read_register(CC1101_REG_RW_FREQ2) & 0x3F; - f = f << 8; - f |= cc1101_spi_read_register(CC1101_REG_RW_FREQ1); - f = f << 8; - f |= cc1101_spi_read_register(CC1101_REG_RW_FREQ0); - return f; + uint32_t freq = cc1101_spi_read_register(CC1101_REG_RW_FREQ2) & CC1101_REG_RW_FREQ2_MASK; + freq = freq << 8; + freq |= cc1101_spi_read_register(CC1101_REG_RW_FREQ1) & CC1101_REG_RW_FREQ1_MASK; + freq = freq << 8; + freq |= cc1101_spi_read_register(CC1101_REG_RW_FREQ0) & CC1101_REG_RW_FREQ0_MASK; + return freq; } void cc1101_set_freq(uint32_t freq) { + cc1101_spi_write_register(CC1101_REG_RW_FREQ0, (uint8_t)(freq) & CC1101_REG_RW_FREQ0_MASK); + freq = freq >> 8; + cc1101_spi_write_register(CC1101_REG_RW_FREQ1, (uint8_t)(freq) & CC1101_REG_RW_FREQ1_MASK); + freq = freq >> 8; + cc1101_spi_write_register(CC1101_REG_RW_FREQ2, (uint8_t)(freq) & CC1101_REG_RW_FREQ2_MASK); } uint64_t cc1101_get_modemcfg(void) { - uint64_t m = cc1101_spi_read_register(CC1101_REG_RW_MDMCFG4); - m = m << 8; - m |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG3); - m = m << 8; - m |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG2); - m = m << 8; - m |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG1) & 0xF3; - m = m << 8; - m |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG0); - return m; + uint64_t cfg = cc1101_spi_read_register(CC1101_REG_RW_MDMCFG4) & CC1101_REG_RW_MDMCFG4_MASK; + cfg = cfg << 8; + cfg |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG3) & CC1101_REG_RW_MDMCFG3_MASK; + cfg = cfg << 8; + cfg |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG2) & CC1101_REG_RW_MDMCFG2_MASK; + cfg = cfg << 8; + cfg |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG1) & CC1101_REG_RW_MDMCFG1_MASK; + cfg = cfg << 8; + cfg |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG0) & CC1101_REG_RW_MDMCFG0_MASK; + return cfg; } -uint8_t cc1101_get_deviatn(void) +void cc1101_set_modemcfg(uint64_t cfg) { - return cc1101_spi_read_register(CC1101_REG_RW_DEVIATN) & 0x77; + cc1101_spi_write_register(CC1101_REG_RW_MDMCFG0, cfg & CC1101_REG_RW_MDMCFG0_MASK); + cfg = cfg >> 8; + cc1101_spi_write_register(CC1101_REG_RW_MDMCFG1, cfg & CC1101_REG_RW_MDMCFG1_MASK); + cfg = cfg >> 8; + cc1101_spi_write_register(CC1101_REG_RW_MDMCFG2, cfg & CC1101_REG_RW_MDMCFG2_MASK); + cfg = cfg >> 8; + cc1101_spi_write_register(CC1101_REG_RW_MDMCFG3, cfg & CC1101_REG_RW_MDMCFG3_MASK); + cfg = cfg >> 8; + cc1101_spi_write_register(CC1101_REG_RW_MDMCFG4, cfg & CC1101_REG_RW_MDMCFG4_MASK); } -void cc1101_set_deviatn(uint8_t dev) +uint8_t cc1101_get_deviatn(void) { + return cc1101_spi_read_register(CC1101_REG_RW_DEVIATN) & CC1101_REG_RW_DEVIATN_MASK; } - -void cc1101_set_modemcfg(uint64_t cfg) +void cc1101_set_deviatn(uint8_t dev) { + cc1101_spi_write_register(CC1101_REG_RW_DEVIATN, dev & CC1101_REG_RW_DEVIATN_MASK); } + uint32_t cc1101_get_mcsm(void) { - uint32_t m = cc1101_spi_read_register(CC1101_REG_RW_MCSM2) & 0x1F; - m = m << 8; - m |= cc1101_spi_read_register(CC1101_REG_RW_MCSM1) & 0x3F; - m = m << 8; - m |= cc1101_spi_read_register(CC1101_REG_RW_MCSM0) & 0x3F; - return m; + uint32_t cfg = cc1101_spi_read_register(CC1101_REG_RW_MCSM2) & CC1101_REG_RW_MCSM2_MASK; + cfg = cfg << 8; + cfg |= cc1101_spi_read_register(CC1101_REG_RW_MCSM1) & CC1101_REG_RW_MCSM1_MASK; + cfg = cfg << 8; + cfg |= cc1101_spi_read_register(CC1101_REG_RW_MCSM0) & CC1101_REG_RW_MCSM0_MASK; + return cfg; } void cc1101_set_mcsm(uint32_t cfg) { + cc1101_spi_write_register(CC1101_REG_RW_MCSM0, cfg & CC1101_REG_RW_MCSM0_MASK); + cfg = cfg >> 8; + cc1101_spi_write_register(CC1101_REG_RW_MCSM1, cfg & CC1101_REG_RW_MCSM1_MASK); + cfg = cfg >> 8; + cc1101_spi_write_register(CC1101_REG_RW_MCSM2, cfg & CC1101_REG_RW_MCSM2_MASK); } uint8_t cc1101_get_foccfg(void) { - return cc1101_spi_read_register(CC1101_REG_RW_FOCCFG) & 0x3F; + return cc1101_spi_read_register(CC1101_REG_RW_FOCCFG) & CC1101_REG_RW_FOCCFG_MASK; } void cc1101_set_foccfg(uint8_t cfg) { + cc1101_spi_write_register(CC1101_REG_RW_FOCCFG, cfg & CC1101_REG_RW_FOCCFG_MASK); } uint8_t cc1101_get_bscfg(void) { - return cc1101_spi_read_register(CC1101_REG_RW_BSCFG); + return cc1101_spi_read_register(CC1101_REG_RW_BSCFG) & CC1101_REG_RW_BSCFG_MASK; } void cc1101_set_bscfg(uint8_t cfg) { + cc1101_spi_write_register(CC1101_REG_RW_BSCFG, cfg & CC1101_REG_RW_BSCFG_MASK); } uint32_t cc1101_get_agcctrl(void) { - uint32_t b = cc1101_spi_read_register(CC1101_REG_RW_AGCCTRL2); - b = b << 8; - b |= cc1101_spi_read_register(CC1101_REG_RW_AGCCTRL1) & 0x7F; - b = b << 8; - b |= cc1101_spi_read_register(CC1101_REG_RW_AGCCTRL0); - return b; + uint32_t ctrl = cc1101_spi_read_register(CC1101_REG_RW_AGCCTRL2) & CC1101_REG_RW_AGCCTRL2_MASK; + ctrl = ctrl << 8; + ctrl |= cc1101_spi_read_register(CC1101_REG_RW_AGCCTRL1) & CC1101_REG_RW_AGCCTRL1_MASK; + ctrl = ctrl << 8; + ctrl |= cc1101_spi_read_register(CC1101_REG_RW_AGCCTRL0) & CC1101_REG_RW_AGCCTRL0_MASK; + return ctrl; } void cc1101_set_agcctrl(uint32_t ctrl) { + cc1101_spi_write_register(CC1101_REG_RW_AGCCTRL0, ctrl & CC1101_REG_RW_AGCCTRL0_MASK); + ctrl = ctrl >> 8; + cc1101_spi_write_register(CC1101_REG_RW_AGCCTRL1, ctrl & CC1101_REG_RW_AGCCTRL1_MASK); + ctrl = ctrl >> 8; + cc1101_spi_write_register(CC1101_REG_RW_AGCCTRL2, ctrl & CC1101_REG_RW_AGCCTRL2_MASK); } uint16_t cc1101_get_worevt(void) { - uint16_t w = cc1101_spi_read_register(CC1101_REG_RW_WOREVT1); - w = w << 8; - w |= cc1101_spi_read_register(CC1101_REG_RW_WOREVT0); - return w; + uint16_t timeout = cc1101_spi_read_register(CC1101_REG_RW_WOREVT1) & CC1101_REG_RW_WOREVT1_MASK; + timeout = timeout << 8; + timeout |= cc1101_spi_read_register(CC1101_REG_RW_WOREVT0) & CC1101_REG_RW_WOREVT0_MASK; + return timeout; } void cc1101_set_worevt(uint16_t timeout) { + cc1101_spi_write_register(CC1101_REG_RW_WOREVT0, timeout & CC1101_REG_RW_WOREVT0_MASK); + timeout = timeout >> 8; + cc1101_spi_write_register(CC1101_REG_RW_WOREVT1, timeout & CC1101_REG_RW_WOREVT1_MASK); } uint8_t cc1101_get_worctrl(void) { - return cc1101_spi_read_register(CC1101_REG_RW_WORCTRL) & 0xFB; + return cc1101_spi_read_register(CC1101_REG_RW_WORCTRL) & CC1101_REG_RW_WORCTRL_MASK; } void cc1101_set_worctrl(uint8_t ctrl) { + cc1101_spi_write_register(CC1101_REG_RW_WORCTRL, ctrl & CC1101_REG_RW_WORCTRL_MASK); } uint16_t cc1101_get_frend(void) { - uint16_t f = cc1101_spi_read_register(CC1101_REG_RW_FREND1); - f = f << 8; - f |= cc1101_spi_read_register(CC1101_REG_RW_FREND0) & 0x37; - return f; + uint16_t cfg = cc1101_spi_read_register(CC1101_REG_RW_FREND1) & CC1101_REG_RW_FREND1_MASK; + cfg = cfg << 8; + cfg |= cc1101_spi_read_register(CC1101_REG_RW_FREND0) & CC1101_REG_RW_FREND0_MASK; + return cfg; } void cc1101_set_frend(uint16_t cfg) { + cc1101_spi_write_register(CC1101_REG_RW_FREND0, cfg & CC1101_REG_RW_FREND0_MASK); + cfg = cfg >> 8; + cc1101_spi_write_register(CC1101_REG_RW_FREND1, cfg & CC1101_REG_RW_FREND1_MASK); } uint32_t cc1101_get_fscal(void) { - uint32_t f = cc1101_spi_read_register(CC1101_REG_RW_FSCAL3); - f = f << 8; - f = cc1101_spi_read_register(CC1101_REG_RW_FSCAL2) & 0x3F; - f = f << 8; - f |= cc1101_spi_read_register(CC1101_REG_RW_FSCAL1) & 0x3F; - f = f << 8; - f |= cc1101_spi_read_register(CC1101_REG_RW_FSCAL0) & 0x7F; - return f; + uint32_t cal = cc1101_spi_read_register(CC1101_REG_RW_FSCAL3) & CC1101_REG_RW_FSCAL3_MASK; + cal = cal << 8; + cal = cc1101_spi_read_register(CC1101_REG_RW_FSCAL2) & CC1101_REG_RW_FSCAL2_MASK; + cal = cal << 8; + cal |= cc1101_spi_read_register(CC1101_REG_RW_FSCAL1) & CC1101_REG_RW_FSCAL1_MASK; + cal = cal << 8; + cal |= cc1101_spi_read_register(CC1101_REG_RW_FSCAL0) & CC1101_REG_RW_FSCAL0_MASK; + return cal; } void cc1101_set_fscal(uint32_t cal) { + cc1101_spi_write_register(CC1101_REG_RW_FSCAL0, cal & CC1101_REG_RW_FSCAL0_MASK); + cal = cal >> 8; + cc1101_spi_write_register(CC1101_REG_RW_FSCAL1, cal & CC1101_REG_RW_FSCAL1_MASK); + cal = cal >> 8; + cc1101_spi_write_register(CC1101_REG_RW_FSCAL2, cal & CC1101_REG_RW_FSCAL2_MASK); + cal = cal >> 8; + cc1101_spi_write_register(CC1101_REG_RW_FSCAL3, cal & CC1101_REG_RW_FSCAL3_MASK); } uint16_t cc1101_get_rcctrl(void) { - uint16_t r = cc1101_spi_read_register(CC1101_REG_RW_RCCTRL1) & 0x7F; - r = r << 8; - r |= cc1101_spi_read_register(CC1101_REG_RW_RCCTRL0) & 0x7F; - return r; + uint16_t ctrl = cc1101_spi_read_register(CC1101_REG_RW_RCCTRL1) & CC1101_REG_RW_RCCTRL1_MASK; + ctrl = ctrl << 8; + ctrl |= cc1101_spi_read_register(CC1101_REG_RW_RCCTRL0) & CC1101_REG_RW_RCCTRL0_MASK; + return ctrl; } void cc1101_set_rcctrl(uint16_t ctrl) { + cc1101_spi_write_register(CC1101_REG_RW_RCCTRL0, ctrl & CC1101_REG_RW_RCCTRL0_MASK); + ctrl = ctrl >> 8; + cc1101_spi_write_register(CC1101_REG_RW_RCCTRL1, ctrl & CC1101_REG_RW_RCCTRL1_MASK); } uint8_t cc1101_get_fstest(void) { - return cc1101_spi_read_register(CC1101_REG_RW_FSTEST); + return cc1101_spi_read_register(CC1101_REG_RW_FSTEST) & CC1101_REG_RW_FSTEST_MASK; } void cc1101_set_fstest(uint8_t test) { + cc1101_spi_write_register(CC1101_REG_RW_FSTEST, test & CC1101_REG_RW_FSTEST_MASK); } uint8_t cc1101_get_ptest(void) { - return cc1101_spi_read_register(CC1101_REG_RW_PTEST); + return cc1101_spi_read_register(CC1101_REG_RW_PTEST) & CC1101_REG_RW_PTEST_MASK; } void cc1101_set_ptest(uint8_t test) { + cc1101_spi_write_register(CC1101_REG_RW_PTEST, test & CC1101_REG_RW_PTEST_MASK); } uint8_t cc1101_get_agctest(void) { - return cc1101_spi_read_register(CC1101_REG_RW_AGCTEST); + return cc1101_spi_read_register(CC1101_REG_RW_AGCTEST) & CC1101_REG_RW_AGCTEST_MASK; } void cc1101_set_agctest(uint8_t test) { + cc1101_spi_write_register(CC1101_REG_RW_AGCTEST, test & CC1101_REG_RW_AGCTEST_MASK); } uint8_t cc1101_get_test0(void) { - return cc1101_spi_read_register(CC1101_REG_RW_TEST0); + return cc1101_spi_read_register(CC1101_REG_RW_TEST0) & CC1101_REG_RW_TEST0_MASK; } void cc1101_set_test0(uint8_t test) { + cc1101_spi_write_register(CC1101_REG_RW_TEST0, test & CC1101_REG_RW_TEST0_MASK); } uint8_t cc1101_get_test1(void) { - return cc1101_spi_read_register(CC1101_REG_RW_TEST1); + return cc1101_spi_read_register(CC1101_REG_RW_TEST1) & CC1101_REG_RW_TEST1_MASK; } void cc1101_set_test1(uint8_t test) { + cc1101_spi_write_register(CC1101_REG_RW_TEST1, test & CC1101_REG_RW_TEST1_MASK); } uint8_t cc1101_get_test2(void) { - return cc1101_spi_read_register(CC1101_REG_RW_TEST2); + return cc1101_spi_read_register(CC1101_REG_RW_TEST2) & CC1101_REG_RW_TEST2_MASK; } void cc1101_set_test2(uint8_t test) { + cc1101_spi_write_register(CC1101_REG_RW_TEST2, test & CC1101_REG_RW_TEST2_MASK); } uint8_t cc1101_get_partnum(void) { - return cc1101_spi_read_register(CC1101_REG_RO_PARTNUM); + return cc1101_spi_read_register(CC1101_REG_RO_PARTNUM) & CC1101_REG_RO_PARTNUM_MASK; } uint8_t cc1101_get_chip_version(void) { - return cc1101_spi_read_register(CC1101_REG_RO_VERSION); + return cc1101_spi_read_register(CC1101_REG_RO_VERSION) & CC1101_REG_RO_VERSION_MASK; } uint8_t cc1101_get_freq_offset_est(void) { - return cc1101_spi_read_register(CC1101_REG_RO_FREQUEST); + return cc1101_spi_read_register(CC1101_REG_RO_FREQUEST) & CC1101_REG_RO_FREQUEST_MASK; } uint8_t cc1101_get_lqi(void) { - return cc1101_spi_read_register(CC1101_REG_RO_LQI); + return cc1101_spi_read_register(CC1101_REG_RO_LQI) & CC1101_REG_RO_LQI_MASK; } int8_t cc1101_get_rssi(void) { - return (int8_t)cc1101_spi_read_register(CC1101_REG_RO_RSSI); + return (int8_t)cc1101_spi_read_register(CC1101_REG_RO_RSSI) & CC1101_REG_RO_RSSI_MASK; +} + +uint8_t cc1101_get_marcstate(void) +{ + return cc1101_spi_read_register(CC1101_REG_RO_MARCSTATE) & CC1101_REG_RO_MARCSTATE_MASK; } uint16_t cc1101_get_wortime(void) { - uint16_t w = cc1101_spi_read_register(CC1101_REG_RO_WORTIME1); + uint16_t w = cc1101_spi_read_register(CC1101_REG_RO_WORTIME1) & CC1101_REG_RO_WORTIME1_MASK; w = w << 8; - w |= cc1101_spi_read_register(CC1101_REG_RO_WORTIME0); + w |= cc1101_spi_read_register(CC1101_REG_RO_WORTIME0) & CC1101_REG_RO_WORTIME0_MASK; return w; } uint8_t cc1101_get_pkt_status(void) { - return cc1101_spi_read_register(CC1101_REG_RO_PKTSTATUS); + return cc1101_spi_read_register(CC1101_REG_RO_PKTSTATUS) & CC1101_REG_RO_PKTSTATUS_MASK; } uint8_t cc1101_get_tx_bytes(void) { - return cc1101_spi_read_register(CC1101_REG_RO_TXBYTES); + return cc1101_spi_read_register(CC1101_REG_RO_TXBYTES) & CC1101_REG_RO_TXBYTES_MASK; } uint8_t cc1101_get_rx_bytes(void) { - return cc1101_spi_read_register(CC1101_REG_RO_RXBYTES); + return cc1101_spi_read_register(CC1101_REG_RO_RXBYTES) & CC1101_REG_RO_RXBYTES_MASK; } +uint8_t cc1101_get_rcctrl0_status(void) +{ + return cc1101_spi_read_register(CC1101_REG_RO_RCCTRL0_STATUS) & CC1101_REG_RO_RCCTRL0_STATUS_MASK; +} + +uint8_t cc1101_get_rcctrl1_status(void) +{ + return cc1101_spi_read_register(CC1101_REG_RO_RCCTRL1_STATUS) & CC1101_REG_RO_RCCTRL1_STATUS_MASK; +} + + + static char* cc1101_config_reg_to_string(uint8_t addr) { switch(addr) { @@ -675,19 +781,3 @@ void cc1101_dump_register(void) } printf("\r\n"); } - -uint32_t cc1101_get_freq_hz(void) -{ - return (uint32_t)((float)(cc1101_get_freq()) * drv.freq_corr); -} - -void cc1101_set_freq_hz(uint32_t hz) -{ - uint32_t freq = (uint32_t)((float)hz / drv.freq_corr); - if(freq <= 0x3FFFFF) - - // TODO: this is only allowed in idle mode - cc1101_spi_write_register(CC1101_REG_RW_FREQ0, freq & 0xFF); - cc1101_spi_write_register(CC1101_REG_RW_FREQ1, (freq >> 8) & 0xFF); - cc1101_spi_write_register(CC1101_REG_RW_FREQ2, (freq >> 16) & 0x3F); -} diff --git a/software/avr.lib/cc1101.h b/software/avr.lib/cc1101.h index 6b981b8..48454b6 100644 --- a/software/avr.lib/cc1101.h +++ b/software/avr.lib/cc1101.h @@ -39,6 +39,8 @@ typedef struct { float freq_corr; } cc1101_driver_conf_t; +// high level interface + void cc1101_init(cc1101_driver_conf_t conf); void cc1101_reg_init(void); void cc1101_soft_reset(void); @@ -52,6 +54,12 @@ void cc1101_rx(void); void cc1101_tx(void); cc1101_state_t cc1101_get_state(void); +uint32_t cc1101_get_freq_hz(void); +void cc1101_set_freq_hz(uint32_t hz); + + +// normalized register access + uint8_t cc1101_get_iocfg0(void); void cc1101_set_iocfg0(uint8_t iocfg); uint8_t cc1101_get_iocfg1(void); @@ -123,15 +131,14 @@ uint8_t cc1101_get_chip_version(void); uint8_t cc1101_get_freq_offset_est(void); uint8_t cc1101_get_lqi(void); int8_t cc1101_get_rssi(void); +uint8_t cc1101_get_marcstate(void); uint16_t cc1101_get_wortime(void); uint8_t cc1101_get_pkt_status(void); uint8_t cc1101_get_tx_bytes(void); uint8_t cc1101_get_rx_bytes(void); +uint8_t cc1101_get_rcctrl0_status(void); +uint8_t cc1101_get_rcctrl1_status(void); void cc1101_dump_register(void); - -uint32_t cc1101_get_freq_hz(void); -void cc1101_set_freq_hz(uint32_t hz); - #endif diff --git a/software/avr.lib/cc1101_defines.h b/software/avr.lib/cc1101_defines.h index 76a632b..f1e63aa 100644 --- a/software/avr.lib/cc1101_defines.h +++ b/software/avr.lib/cc1101_defines.h @@ -169,4 +169,68 @@ #define CC1101_GDO_CFG_3STATE 0x2E + +//register masks +#define CC1101_REG_RW_IOCFG2_MASK 0x7F +#define CC1101_REG_RW_IOCFG1_MASK 0xFF +#define CC1101_REG_RW_IOCFG0_MASK 0xFF +#define CC1101_REG_RW_FIFOTHR_MASK 0x7F +#define CC1101_REG_RW_SYNC1_MASK 0xFF +#define CC1101_REG_RW_SYNC0_MASK 0xFF +#define CC1101_REG_RW_PKTLEN_MASK 0xFF +#define CC1101_REG_RW_PKTCTRL1_MASK 0xEF +#define CC1101_REG_RW_PKTCTRL0_MASK 0x77 +#define CC1101_REG_RW_ADDR_MASK 0xFF +#define CC1101_REG_RW_CHANNR_MASK 0xFF +#define CC1101_REG_RW_FSCTRL1_MASK 0x1F +#define CC1101_REG_RW_FSCTRL0_MASK 0xFF +#define CC1101_REG_RW_FREQ2_MASK 0x3F +#define CC1101_REG_RW_FREQ1_MASK 0xFF +#define CC1101_REG_RW_FREQ0_MASK 0xFF +#define CC1101_REG_RW_MDMCFG4_MASK 0xFF +#define CC1101_REG_RW_MDMCFG3_MASK 0xFF +#define CC1101_REG_RW_MDMCFG2_MASK 0xFF +#define CC1101_REG_RW_MDMCFG1_MASK 0xF3 +#define CC1101_REG_RW_MDMCFG0_MASK 0xFF +#define CC1101_REG_RW_DEVIATN_MASK 0x77 +#define CC1101_REG_RW_MCSM2_MASK 0x1F +#define CC1101_REG_RW_MCSM1_MASK 0x3F +#define CC1101_REG_RW_MCSM0_MASK 0x3F +#define CC1101_REG_RW_FOCCFG_MASK 0x3F +#define CC1101_REG_RW_BSCFG_MASK 0xFF +#define CC1101_REG_RW_AGCCTRL2_MASK 0xFF +#define CC1101_REG_RW_AGCCTRL1_MASK 0x7F +#define CC1101_REG_RW_AGCCTRL0_MASK 0xFF +#define CC1101_REG_RW_WOREVT1_MASK 0xFF +#define CC1101_REG_RW_WOREVT0_MASK 0xFF +#define CC1101_REG_RW_WORCTRL_MASK 0xFB +#define CC1101_REG_RW_FREND1_MASK 0xFF +#define CC1101_REG_RW_FREND0_MASK 0x37 +#define CC1101_REG_RW_FSCAL3_MASK 0xFF +#define CC1101_REG_RW_FSCAL2_MASK 0x3F +#define CC1101_REG_RW_FSCAL1_MASK 0x3F +#define CC1101_REG_RW_FSCAL0_MASK 0x7F +#define CC1101_REG_RW_RCCTRL1_MASK 0x7F +#define CC1101_REG_RW_RCCTRL0_MASK 0x7F +#define CC1101_REG_RW_FSTEST_MASK 0xFF +#define CC1101_REG_RW_PTEST_MASK 0xFF +#define CC1101_REG_RW_AGCTEST_MASK 0xFF +#define CC1101_REG_RW_TEST2_MASK 0xFF +#define CC1101_REG_RW_TEST1_MASK 0xFF +#define CC1101_REG_RW_TEST0_MASK 0xFF +#define CC1101_REG_RO_PARTNUM_MASK 0xFF +#define CC1101_REG_RO_VERSION_MASK 0xFF +#define CC1101_REG_RO_FREQUEST_MASK 0xFF +#define CC1101_REG_RO_LQI_MASK 0xFF +#define CC1101_REG_RO_RSSI_MASK 0xFF +#define CC1101_REG_RO_MARCSTATE_MASK 0x1F +#define CC1101_REG_RO_WORTIME1_MASK 0xFF +#define CC1101_REG_RO_WORTIME0_MASK 0xFF +#define CC1101_REG_RO_PKTSTATUS_MASK 0xFF +#define CC1101_REG_RO_VCO_VC_DAC_MASK 0xFF +#define CC1101_REG_RO_TXBYTES_MASK 0xFF +#define CC1101_REG_RO_RXBYTES_MASK 0xFF +#define CC1101_REG_RO_RCCTRL1_STATUS_MASK 0x7F +#define CC1101_REG_RO_RCCTRL0_STATUS_MASK 0x7F + #endif -- cgit v1.2.3