diff options
Diffstat (limited to 'software/hhd70dongle/c1101lib.c')
| -rw-r--r-- | software/hhd70dongle/c1101lib.c | 204 |
1 files changed, 102 insertions, 102 deletions
diff --git a/software/hhd70dongle/c1101lib.c b/software/hhd70dongle/c1101lib.c index 61780d5..02ec5fc 100644 --- a/software/hhd70dongle/c1101lib.c +++ b/software/hhd70dongle/c1101lib.c @@ -33,7 +33,7 @@ #include <util/delay.h> #include "c1101lib.h" -#include "spi.h" +#include "hhd70.h" #include "usb_rawhid.h" #include "util.h" @@ -41,14 +41,14 @@ #define SPIC1101_MAX_WAIT 21 -int16_t spi_c1101_write_byte_ok_get_status(char data) +int16_t c1101_spi_write_byte_ok_get_status(char data) { //~ uint8_t debug_sb[6]; char sb; unsigned int attempts = 0; do { - sb = spi_exchange_byte(data); + sb = hhd70_spi_exchange_byte(data); //Note: content of returned StatusByte is actually context depenedant on sent command // i.e. we won't get Fifo Byte count or overflow status on normal command and so on // e.g. we only get TX Fifo Free Byte count while writing to TX Fifo @@ -62,118 +62,118 @@ int16_t spi_c1101_write_byte_ok_get_status(char data) return sb; } -int16_t spi_c1101_strobe_command(char address) +int16_t c1101_spi_strobe_command(char address) { char rbyte; if (address < 0x30) return -1; - spi_cs_enable(); - spi_c1101_wait_chip_rdy(); + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); //POST DEBUG: don't return anything - rbyte = spi_c1101_write_byte_ok_get_status(address); + rbyte = c1101_spi_write_byte_ok_get_status(address); if (rbyte < 0) return -1; - spi_cs_disable(); + hhd70_spi_cs_disable(); return rbyte; } // note addresses range from 0x00 to 0x2F for normal registers and 0xF0 to 0xFD for special status registers -int16_t spi_c1101_read_register(char address) +int16_t c1101_spi_read_register(char address) { char rbyte; if (address < 0x30) address |= 0x80; else address |= 0xC0; - spi_cs_enable(); - spi_c1101_wait_chip_rdy(); - if (spi_c1101_write_byte_ok_get_status(address) < 0) + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + if (c1101_spi_write_byte_ok_get_status(address) < 0) return -1; - rbyte = spi_read_byte(); - spi_cs_disable(); + rbyte = hhd70_spi_read_byte(); + hhd70_spi_cs_disable(); return rbyte; } // note addresses range from 0x00 to 0x2F for normal registers -int16_t spi_c1101_write_register(char address, char byte) +int16_t c1101_spi_write_register(char address, char byte) { - spi_cs_enable(); - spi_c1101_wait_chip_rdy(); - if (spi_c1101_write_byte_ok_get_status(address & 0x2F) < 0) + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + if (c1101_spi_write_byte_ok_get_status(address & 0x2F) < 0) return -1; _delay_ms(2); - if (spi_c1101_write_byte_ok_get_status(byte) < 0) + if (c1101_spi_write_byte_ok_get_status(byte) < 0) return -1; - spi_cs_disable(); + hhd70_spi_cs_disable(); return 1; } -void spi_c1101_dump_registers_to_usb(void) +void c1101_spi_dump_registers_to_usb(void) { int c = 0; uint8_t debug_sb[6]; - spi_cs_enable(); - spi_c1101_wait_chip_rdy(); - if (spi_c1101_write_byte_ok_get_status(0xC0) < 0) + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + if (c1101_spi_write_byte_ok_get_status(0xC0) < 0) return; usb_rawhid_send((uint8_t*)"dump all 46 registers:",255); for (c=0; c<47; c++) { - debug_sprint_int16hex(debug_sb, spi_read_byte()); + debug_sprint_int16hex(debug_sb, hhd70_spi_read_byte()); usb_rawhid_send(debug_sb,255); } - spi_cs_disable(); + hhd70_spi_cs_disable(); } -int spi_c1101_read_rxfifo(int leave_num_bytes, char *buffer, int maxlen) +int c1101_spi_read_rxfifo(int leave_num_bytes, char *buffer, int maxlen) { int num_read = 0; uint8_t num_available = 0; - spi_cs_enable(); - spi_c1101_wait_chip_rdy(); - if (spi_c1101_write_byte_ok_get_status(SPIC1101_ADDR_RXBYTES) < 0) + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_RXBYTES) < 0) return -1; - num_available = spi_read_byte(); + num_available = hhd70_spi_read_byte(); if (num_available == 0) return 0; - if (spi_c1101_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST) < 0) + if (c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST) < 0) return -1; while (maxlen-- > 0 && num_available - num_read > leave_num_bytes) { - buffer[num_read++] = spi_read_byte(); + buffer[num_read++] = hhd70_spi_read_byte(); } - spi_cs_disable(); + hhd70_spi_cs_disable(); return num_read; } //note: currently this function reads at most 15 bytes -int spi_c1101_read_rxfifo_max15(int leave_num_bytes, char *buffer, int maxlen) +int c1101_spi_read_rxfifo_max15(int leave_num_bytes, char *buffer, int maxlen) { int16_t sb; int num_read = 0; - spi_cs_enable(); - spi_c1101_wait_chip_rdy(); - sb = spi_c1101_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST); + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_READ_BURST); if (sb < 0) return -1; //note if SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) == 15 then 15 or more bytes are available while (maxlen-- > 0 && SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb) - num_read > leave_num_bytes) { //hope this works !! - buffer[num_read++] = spi_read_byte(); + buffer[num_read++] = hhd70_spi_read_byte(); } - spi_cs_disable(); + hhd70_spi_cs_disable(); return num_read; } //note: always check if num_written returned == len given -int spi_c1101_write_txfifo(char *buffer, int len) +int c1101_spi_write_txfifo(char *buffer, int len) { char sb; int num_written = 0; - spi_cs_enable(); - spi_c1101_wait_chip_rdy(); - sb = spi_c1101_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_WRITE_BURST); + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_FIFO_WRITE_BURST); if (sb < 0) return -1; //~ uint8_t debug_sb[6]; @@ -182,9 +182,9 @@ int spi_c1101_write_txfifo(char *buffer, int len) //~ usb_rawhid_send((uint8_t*)"TXFifo bytes available",255); //~ debug_sprint_int16hex(debug_sb, SPIC1101_SB_FIFO_BYTES_AVAILABLE(sb)); //~ usb_rawhid_send(debug_sb,255); - sb = spi_c1101_write_byte_ok_get_status(buffer[num_written++]); + sb = c1101_spi_write_byte_ok_get_status(buffer[num_written++]); } - spi_cs_disable(); + hhd70_spi_cs_disable(); return num_written; } @@ -195,49 +195,49 @@ int spi_c1101_write_txfifo(char *buffer, int len) void c1101_init(void) { //reset C1101 - spi_c1101_strobe_command(SPIC1101_ADDR_SRES); + c1101_spi_strobe_command(SPIC1101_ADDR_SRES); _delay_ms(100); //flush FIFOs - spi_c1101_strobe_command(SPIC1101_ADDR_SFRX); - spi_c1101_strobe_command(SPIC1101_ADDR_SFTX); + c1101_spi_strobe_command(SPIC1101_ADDR_SFRX); + c1101_spi_strobe_command(SPIC1101_ADDR_SFTX); //dump pre-init default values to usb - spi_c1101_dump_registers_to_usb(); + c1101_spi_dump_registers_to_usb(); //enable analog temperature sensor on GDO0 - spi_c1101_write_register(SPIC1101_ADDR_IOCFG0, 0x80); + c1101_spi_write_register(SPIC1101_ADDR_IOCFG0, 0x80); //enable RX FIFO interrupt (i.e. GPO2 pulls high if >= FIFOTHR bytes are in RX FIFO) - spi_c1101_write_register(SPIC1101_ADDR_IOCFG2, 0); + c1101_spi_write_register(SPIC1101_ADDR_IOCFG2, 0); // FIFOTHR RX FIFO and TX FIFO Thresholds // pull GPO high (interrupt) if more than 12 bytes in rx buffer (or less than 53 in tx) - spi_c1101_write_register(SPIC1101_ADDR_FIFOTHR, 2); + c1101_spi_write_register(SPIC1101_ADDR_FIFOTHR, 2); // PKTCTRL0 Packet Automation Control - //spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode - spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) - spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet + //c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000010); //crc disabled; use FIFOs; infinite packet length mode + c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) + c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL1, 0x00); //no address check, no append rssi and crc_ok to packet // FSCTRL1 Frequency Synthesizer Control - spi_c1101_write_register(SPIC1101_ADDR_FSCTRL1, 0x06); + c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, 0x06); // FREQn Frequency Control Words - spi_c1101_write_register(SPIC1101_ADDR_FREQ2, 0x10); //should be 435.125 mhz - spi_c1101_write_register(SPIC1101_ADDR_FREQ1, 0xBF); - spi_c1101_write_register(SPIC1101_ADDR_FREQ0, 0xEF); - spi_c1101_write_register(SPIC1101_ADDR_FSCTRL0, 0); //frequency offset + c1101_spi_write_register(SPIC1101_ADDR_FREQ2, 0x10); //should be 435.125 mhz + c1101_spi_write_register(SPIC1101_ADDR_FREQ1, 0xBF); + c1101_spi_write_register(SPIC1101_ADDR_FREQ0, 0xEF); + c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, 0); //frequency offset // MDMCFGn Modem Configuration - spi_c1101_write_register(SPIC1101_ADDR_MDMCFG4, 0xF8); - spi_c1101_write_register(SPIC1101_ADDR_MDMCFG3, 0x83); - spi_c1101_write_register(SPIC1101_ADDR_MDMCFG2, 0x13); - spi_c1101_write_register(SPIC1101_ADDR_MDMCFG1, 0x00); + c1101_spi_write_register(SPIC1101_ADDR_MDMCFG4, 0xF8); + c1101_spi_write_register(SPIC1101_ADDR_MDMCFG3, 0x83); + c1101_spi_write_register(SPIC1101_ADDR_MDMCFG2, 0x13); + c1101_spi_write_register(SPIC1101_ADDR_MDMCFG1, 0x00); // DEVIATN Modem Deviation Setting - spi_c1101_write_register(SPIC1101_ADDR_DEVIATN, 0x07); + c1101_spi_write_register(SPIC1101_ADDR_DEVIATN, 0x07); // MCSM0 Main Radio Control State Machine Configuration - spi_c1101_write_register(SPIC1101_ADDR_MCSM0, 0x18); + c1101_spi_write_register(SPIC1101_ADDR_MCSM0, 0x18); // FOCCFG Frequency Offset Compensation Configuration - spi_c1101_write_register(SPIC1101_ADDR_FOCCFG, 0x16); + c1101_spi_write_register(SPIC1101_ADDR_FOCCFG, 0x16); // WORCTRL Wake On Radio Control - spi_c1101_write_register(SPIC1101_ADDR_WORCTRL, 0xFB); + c1101_spi_write_register(SPIC1101_ADDR_WORCTRL, 0xFB); // FSCALn Frequency Synthesizer Calibration - spi_c1101_write_register(SPIC1101_ADDR_FSCAL3, 0xE9); - spi_c1101_write_register(SPIC1101_ADDR_FSCAL2, 0x2A); - spi_c1101_write_register(SPIC1101_ADDR_FSCAL1, 0x00); - spi_c1101_write_register(SPIC1101_ADDR_FSCAL0, 0x1F); + c1101_spi_write_register(SPIC1101_ADDR_FSCAL3, 0xE9); + c1101_spi_write_register(SPIC1101_ADDR_FSCAL2, 0x2A); + c1101_spi_write_register(SPIC1101_ADDR_FSCAL1, 0x00); + c1101_spi_write_register(SPIC1101_ADDR_FSCAL0, 0x1F); // note: for now: assume f_xosc to be 26 Mhz // for ~433.125 Mhz -> freq = 1091741, freq_offset = 0 @@ -258,21 +258,21 @@ void c1101_setFrequency(uint32_t freq, uint8_t freq_offset, uint8_t if_freq) } while (! (SPIC1101_SB_IDLE(sb))); //programm frequency usb_rawhid_send((uint8_t*)"setting frequency",255); - spi_c1101_write_register(SPIC1101_ADDR_FREQ0, freq & 0xFF); - spi_c1101_write_register(SPIC1101_ADDR_FREQ1, (freq >> 8) & 0xFF); - spi_c1101_write_register(SPIC1101_ADDR_FREQ2, (freq >> 16) & 0x3F); + c1101_spi_write_register(SPIC1101_ADDR_FREQ0, freq & 0xFF); + c1101_spi_write_register(SPIC1101_ADDR_FREQ1, (freq >> 8) & 0xFF); + c1101_spi_write_register(SPIC1101_ADDR_FREQ2, (freq >> 16) & 0x3F); //set frequency offset - spi_c1101_write_register(SPIC1101_ADDR_FSCTRL0, freq_offset); - //spi_c1101_write_register(SPIC1101_ADDR_FSCTRL1, if_freq & 0x1F); + c1101_spi_write_register(SPIC1101_ADDR_FSCTRL0, freq_offset); + //c1101_spi_write_register(SPIC1101_ADDR_FSCTRL1, if_freq & 0x1F); //set channel 0 - spi_c1101_write_register(SPIC1101_ADDR_CHANNR, 0); + c1101_spi_write_register(SPIC1101_ADDR_CHANNR, 0); } char c1101_putToSleep(void) { - return spi_c1101_strobe_command(SPIC1101_ADDR_SPWD); + return c1101_spi_strobe_command(SPIC1101_ADDR_SPWD); } @@ -280,11 +280,11 @@ uint16_t c1101_measureTemp(void) { uint16_t temp; char ptest_value=0x7F; - ptest_value = spi_c1101_read_register(SPIC1101_ADDR_PTEST); - spi_c1101_write_register(SPIC1101_ADDR_PTEST, 0xBF); + ptest_value = c1101_spi_read_register(SPIC1101_ADDR_PTEST); + c1101_spi_write_register(SPIC1101_ADDR_PTEST, 0xBF); _delay_ms(5); temp = adc_read(ADCMUX_INTERNALTEMP); - spi_c1101_write_register(SPIC1101_ADDR_PTEST, ptest_value); + c1101_spi_write_register(SPIC1101_ADDR_PTEST, ptest_value); return temp; } @@ -293,13 +293,13 @@ void c1101_handleStatusByte(char sb) //on RXFifo Overflow, Flush RX Fifo if (SPIC1101_SB_RXFIFO_OVERFLOW(sb)) { - spi_c1101_strobe_command(SPIC1101_ADDR_SFRX); + c1101_spi_strobe_command(SPIC1101_ADDR_SFRX); usb_rawhid_send((uint8_t*)"RX fifo flushed",255); } //on TXFifo Overflow, Flush TX Fifo if (SPIC1101_SB_TXFIFO_OVERFLOW(sb)) { - spi_c1101_strobe_command(SPIC1101_ADDR_SFTX); + c1101_spi_strobe_command(SPIC1101_ADDR_SFTX); usb_rawhid_send((uint8_t*)"TX fifo flushed",255); } } @@ -307,10 +307,10 @@ void c1101_handleStatusByte(char sb) char c1101_getStatus(void) { char sb=0; - spi_cs_enable(); - spi_c1101_wait_chip_rdy(); - sb = spi_c1101_write_byte_ok_get_status(SPIC1101_ADDR_SNOP); - spi_cs_disable(); + hhd70_spi_cs_enable(); + hhd70_c1101_wait_chip_rdy(); + sb = c1101_spi_write_byte_ok_get_status(SPIC1101_ADDR_SNOP); + hhd70_spi_cs_disable(); //debug start uint8_t debug_sb[6]; usb_rawhid_send((uint8_t*)"c1101 status:",255); @@ -324,7 +324,7 @@ char c1101_getStatus(void) char c1101_getMARCState(void) { char sb=0; - sb = spi_c1101_read_register(SPIC1101_ADDR_MARCSTATE); + sb = c1101_spi_read_register(SPIC1101_ADDR_MARCSTATE); sb &= 0x1F; //debug start uint8_t debug_sb[6]; @@ -337,30 +337,30 @@ char c1101_getMARCState(void) uint8_t c1101_getNumBytesInTXFifo(void) { - return spi_c1101_read_register(SPIC1101_ADDR_TXBYTES); + return c1101_spi_read_register(SPIC1101_ADDR_TXBYTES); } void c1101_transmitData(char *buffer, unsigned int len) { uint8_t debug_sb[6]; uint8_t num_written = 0; - uint8_t mcsm1 = spi_c1101_read_register(SPIC1101_ADDR_MCSM1); + uint8_t mcsm1 = c1101_spi_read_register(SPIC1101_ADDR_MCSM1); //configure state machine to automatically go to IDLE, once packet was transmitted mcsm1 = (mcsm1 & 0b11111100) | 0b00; - spi_c1101_write_register(SPIC1101_ADDR_MCSM1, 0x18); - spi_c1101_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) + c1101_spi_write_register(SPIC1101_ADDR_MCSM1, 0x18); + c1101_spi_write_register(SPIC1101_ADDR_PKTCTRL0, 0b0000000001); //crc disabled; use FIFOs; variable packet length mode (first TX FIFO byte must be length) // flush TX FIFO - num_written = spi_c1101_strobe_command(SPIC1101_ADDR_SFTX); + num_written = c1101_spi_strobe_command(SPIC1101_ADDR_SFTX); usb_rawhid_send((uint8_t*)"Flush TX Fifo",255); debug_sprint_int16hex(debug_sb, num_written); usb_rawhid_send(debug_sb,255); num_written = (uint8_t) len; //variable packet length: write length of packet to TX FIFO: - spi_c1101_write_txfifo((char*) &num_written, 1); + c1101_spi_write_txfifo((char*) &num_written, 1); //~ //fill buffer - //~ num_written = spi_c1101_write_txfifo(buffer, len); + //~ num_written = c1101_spi_write_txfifo(buffer, len); //~ buffer += num_written; //~ len -= num_written; @@ -377,8 +377,8 @@ void c1101_transmitData(char *buffer, unsigned int len) //~ usb_rawhid_send(debug_sb,255); //start transmitting - //num_written = spi_c1101_strobe_command(SPIC1101_ADDR_STX); - //~ num_written = spi_exchange_byte(SPIC1101_ADDR_STX); + //num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX); + //~ num_written = hhd70_spi_exchange_byte(SPIC1101_ADDR_STX); //~ usb_rawhid_send((uint8_t*)"Strobe STX",255); //~ debug_sprint_int16hex(debug_sb, num_written); //~ usb_rawhid_send(debug_sb,255); @@ -392,14 +392,14 @@ void c1101_transmitData(char *buffer, unsigned int len) do { c1101_getStatus(); - num_written = spi_c1101_write_txfifo(buffer, len ); + num_written = c1101_spi_write_txfifo(buffer, len ); buffer += num_written; len -= num_written; c1101_state = c1101_getMARCState(); if (c1101_state == 1) { //from idle state, go to RX state - num_written = spi_c1101_strobe_command(SPIC1101_ADDR_STX); + num_written = c1101_spi_strobe_command(SPIC1101_ADDR_STX); //~ usb_rawhid_send((uint8_t*)"Strobe STX",255); //~ debug_sprint_int16hex(debug_sb, num_written); //~ usb_rawhid_send(debug_sb,255); @@ -429,7 +429,7 @@ void c1101_recieveData(void) uint8_t num_leave_in_fifo = 1; do { - num_recv = spi_c1101_read_rxfifo( num_leave_in_fifo, recv_data+num_recv_total, max_len - num_recv_total); + num_recv = c1101_spi_read_rxfifo( num_leave_in_fifo, recv_data+num_recv_total, max_len - num_recv_total); num_recv_total += num_recv; //variable packet length: |