diff options
Diffstat (limited to 'software/avr.lib/util.c')
| -rw-r--r-- | software/avr.lib/util.c | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/software/avr.lib/util.c b/software/avr.lib/util.c index d927f8e..6624699 100644 --- a/software/avr.lib/util.c +++ b/software/avr.lib/util.c @@ -45,8 +45,14 @@ void cpu_init(void) #define BOOTLOADER_VEC 0xFC00 #elif defined(__BOARD_teensy2pp__) #define BOOTLOADER_VEC 0x1FC00 +#elif defined(__BOARD_minimus__) + #define BOOTLOADER_VEC 0x3000 +#elif defined(__BOARD_minimus32__) + #define BOOTLOADER_VEC 0x3800 #elif defined(__BOARD_hhd70dongle__) #define BOOTLOADER_VEC 0x3800 +#else + #define BOOTLOADER_VEC 0x0000 #endif typedef void (*f_ptr_type)(void); @@ -54,7 +60,8 @@ f_ptr_type start_bootloader = (f_ptr_type)BOOTLOADER_VEC; void reset2bootloader(void) { -#if defined(__BOARD_teensy1__) || defined(__BOARD_teensy1pp__) || defined(__BOARD_teensy2__) || defined(__BOARD_teensy2pp__) || defined(__BOARD_hhd70dongle__) +#if defined(__BOARD_teensy1__) || defined(__BOARD_teensy1pp__) || defined(__BOARD_teensy2__) || defined(__BOARD_teensy2pp__) || \ + defined(__BOARD_hhd70dongle__) || defined(__BOARD_minimus__) || defined(__BOARD_minimus32__) cli(); // disable watchdog, if enabled // disable all peripherals @@ -82,6 +89,16 @@ void reset2bootloader(void) TIMSK0 = 0; TIMSK1 = 0; TIMSK2 = 0; TIMSK3 = 0; UCSR1B = 0; TWCR = 0; DDRA = 0; DDRB = 0; DDRC = 0; DDRD = 0; DDRE = 0; DDRF = 0; PORTA = 0; PORTB = 0; PORTC = 0; PORTD = 0; PORTE = 0; PORTF = 0; + #elif defined(__BOARD_minimus__) + EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; + TIMSK0 = 0; TIMSK1 = 0; UCSR1B = 0; + DDRB = 0; DDRC = 0; DDRD = 0; + PORTB = 0; PORTC = 0; PORTD = 0; + #elif defined(__BOARD_minimus32__) + EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; + TIMSK0 = 0; TIMSK1 = 0; UCSR1B = 0; + DDRB = 0; DDRC = 0; DDRD = 0; + PORTB = 0; PORTC = 0; PORTD = 0; #elif defined(__BOARD_hhd70dongle__) EIMSK = 0; PCICR = 0; SPCR = 0; ACSR = 0; EECR = 0; ADCSRA = 0; TIMSK0 = 0; TIMSK1 = 0; TIMSK3 = 0; TIMSK4 = 0; UCSR1B = 0; TWCR = 0; |