diff options
Diffstat (limited to 'software/avr.lib/rda1846_defines.h')
| -rw-r--r-- | software/avr.lib/rda1846_defines.h | 248 |
1 files changed, 248 insertions, 0 deletions
diff --git a/software/avr.lib/rda1846_defines.h b/software/avr.lib/rda1846_defines.h new file mode 100644 index 0000000..968475e --- /dev/null +++ b/software/avr.lib/rda1846_defines.h @@ -0,0 +1,248 @@ +/* + * + * mur.sat + * + * Somewhen in the year 20xx, mur.at will have a nano satellite launched + * into a low earth orbit (310 km above the surface of our planet). The + * satellite itself is a TubeSat personal satellite kit, developed and + * launched by interorbital systems. mur.sat is a joint venture of mur.at, + * ESC im Labor and realraum. + * + * Please visit the project hompage at sat.mur.at for further information. + * + * + * Copyright (C) 2013-2015 Christian Pointner <equinox@mur.at> + * + * This file is part of mur.sat. + * + * mur.sat is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * mur.sat is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with mur.sat. If not, see <http://www.gnu.org/licenses/>. + * + */ + +#ifndef MURSAT_rda1846_defines_h_INCLUDED +#define MURSAT_rda1846_defines_h_INCLUDED + +// TWI +#define RDA1846_CHIP_ADDR 0xE2 +#define RDA1846_ADDR_W (0<<7) +#define RDA1846_ADDR_R (1<<7) +#define RDA1846_ADDR_LIMIT 0x7F + + +// registers +#define RDA1846_REG_CTL 0x30 +#define RDA1846_REG_GPIO 0x1F +#define RDA1846_REG_INT 0x2D +#define RDA1846_REG_FLAG 0x5C +#define RDA1846_REG_RSSI 0x5F +#define RDA1846_REG_VSSI 0x60 + +#define RDA1846_REG_CLK_MODE 0x04 +#define RDA1846_REG_XTAL 0x2B +#define RDA1846_REG_ADCLK 0x2C + +#define RDA1846_REG_RF_BAND 0x0F +#define RDA1846_REG_FREQH 0x29 +#define RDA1846_REG_FREQL 0x2A + +#define RDA1846_REG_PA_BIAS 0x0A +#define RDA1846_REG_TX_VOICE 0x3C +#define RDA1846_REG_VOX_OPEN 0x41 +#define RDA1846_REG_VOX_SHUT 0x42 + +#define RDA1846_REG_RX_VOICE 0x44 +#define RDA1846_REG_SUBAUDIO 0x45 +#define RDA1846_REG_SQ_OPEN 0x48 +#define RDA1846_REG_SQ_SHUT 0x49 + +#define RDA1846_REG_DTMF_CTL 0x63 +#define RDA1846_REG_DTMF_T1 0x35 +#define RDA1846_REG_DTMF_T2 0x36 +#define RDA1846_REG_DTMF_C01 0x66 +#define RDA1846_REG_DTMF_C23 0x67 +#define RDA1846_REG_DTMF_C45 0x68 +#define RDA1846_REG_DTMF_C67 0x69 +#define RDA1846_REG_DTMF_OUT 0x6C + +//freq +#ifdef RDA_QUARTZ_12M288 +#define RDA1846_FREQ_CORR_2M 73.1428567759 +#endif // RDA_QUARTZ_12M288 +#ifdef RDA_QUARTZ_13M +#define RDA1846_FREQ_CORR_2M 69.136878448 +#endif // RDA_QUARTZ_13M + +#define RDA1846_FREQ_CORR_1M5 RDA1846_FREQ_CORR_2M/1.5 +#define RDA1846_FREQ_CORR_70CM RDA1846_FREQ_CORR_2M/3.0 + + +// init values +#define RDA1846_RF_BAND_2M 0x00E4 // select 2m Band +#define RDA1846_BAND_2M_LOW 134000 // kHz +#define RDA1846_BAND_2M_HIGH 174000 // kHZ + +#define RDA1846_RF_BAND_1M5 0x00A4 // select 1.5m Band +#define RDA1846_BAND_1M5_LOW 200000 // kHz +#define RDA1846_BAND_1M5_HIGH 260000 // kHZ + +#define RDA1846_RF_BAND_70CM 0x0024 // select 70cm Band +#define RDA1846_BAND_70CM_LOW 400000 // kHz +#define RDA1846_BAND_70CM_HIGH 520000 // kHZ + +#ifdef RDA_QUARTZ_12M288 +#define RDA1846_XTAL_FREQ 12288 // 12.288 MHz +#define RDA1846_ADCLK_FREQ 6144 // 12.288/2 MHz +#define RDA1846_CLK_MODE 0x0F11 // 12-14 MHz +#endif // RDA_QUARTZ_12M288 + +#ifdef RDA_QUARTZ_13M +#define RDA1846_XTAL_FREQ 13000 // 13.000 MHz +#define RDA1846_ADCLK_FREQ 6500 // 13.000/2 MHz +#define RDA1846_CLK_MODE 0x0F11 // 12-14 MHz +#endif // RDA_QUARTZ_13M + + + + +// ctl +#define RDA1846_CTL_CH_25K 0x3000 +#define RDA1846_CTL_CH_12K5 0x0000 +#define RDA1846_CTL_CH_RESET 0xCFFF + +#define RDA1846_CTL_TAIL_ELIM 0x0800 + +#define RDA1846_CTL_RX_A_TX_A 0x0200 +#define RDA1846_CTL_RX_A_TX_M 0x0100 +#define RDA1846_CTL_RX_M_TX_M 0x0000 + +#define RDA1846_CTL_MUTE 0x0080 +#define RDA1846_CTL_TX 0x0040 +#define RDA1846_CTL_RX 0x0020 +#define RDA1846_CTL_VOX 0x0010 +#define RDA1846_CTL_SQ 0x0008 +#define RDA1846_CTL_PDN 0x0004 +#define RDA1846_CTL_CHIP_CAL 0x0002 +#define RDA1846_CTL_SOFT_RST 0x0001 + + +// flag +#define RDA1846_FLAG_DTMF_IDLE 0x1000 +#define RDA1846_FLAG_RXON_RF 0x0400 +#define RDA1846_FLAG_TXON_RF 0x0200 +#define RDA1846_FLAG_INVERT_DET 0x0080 +#define RDA1846_FLAG_CSS_CMP 0x0004 +#define RDA1846_FLAG_SQ 0x0002 +#define RDA1846_FLAG_VOX 0x0001 + +#define RDA1846_FLAGS_MASK 0x1687 + + +// gpio +#define RDA1846_GPIO_7_HI_Z 0x0000 +#define RDA1846_GPIO_7_VOX 0x4000 +#define RDA1846_GPIO_7_LOW 0x8000 +#define RDA1846_GPIO_7_HIGH 0xC000 + +#define RDA1846_GPIO_6_HI_Z 0x0000 +#define RDA1846_GPIO_6_SQ 0x1000 +#define RDA1846_GPIO_6_LOW 0x2000 +#define RDA1846_GPIO_6_HIGH 0x3000 + +#define RDA1846_GPIO_5_HI_Z 0x0000 +#define RDA1846_GPIO_5_TXON_RF 0x0400 +#define RDA1846_GPIO_5_LOW 0x0800 +#define RDA1846_GPIO_5_HIGH 0x0C00 + +#define RDA1846_GPIO_4_HI_Z 0x0000 +#define RDA1846_GPIO_4_RXON_RF 0x0100 +#define RDA1846_GPIO_4_LOW 0x0200 +#define RDA1846_GPIO_4_HIGH 0x0300 + +#define RDA1846_GPIO_3_HI_Z 0x0000 +#define RDA1846_GPIO_3_SDO 0x0040 +#define RDA1846_GPIO_3_LOW 0x0080 +#define RDA1846_GPIO_3_HIGH 0x00C0 + +#define RDA1846_GPIO_2_HI_Z 0x0000 +#define RDA1846_GPIO_2_INT 0x0010 +#define RDA1846_GPIO_2_LOW 0x0020 +#define RDA1846_GPIO_2_HIGH 0x0030 + +#define RDA1846_GPIO_1_HI_Z 0x0000 +#define RDA1846_GPIO_1_CODE 0x0004 +#define RDA1846_GPIO_1_LOW 0x0008 +#define RDA1846_GPIO_1_HIGH 0x000C + +#define RDA1846_GPIO_0_HI_Z 0x0000 +#define RDA1846_GPIO_0_CSS 0x0001 +#define RDA1846_GPIO_0_LOW 0x0002 +#define RDA1846_GPIO_0_HIGH 0x0003 + + +// int +#define RDA1846_INT_CSS_CMP 0x0200 +#define RDA1846_INT_RXON_RF 0x0100 +#define RDA1846_INT_TXON_RF 0x0080 +#define RDA1846_INT_DTMF_IDLE 0x0040 +#define RDA1846_INT_INVERT_DET 0x0020 +#define RDA1846_INT_IDLE_TO 0x0010 +#define RDA1846_INT_RXON_RF_TO 0x0008 +#define RDA1846_INT_SQ 0x0004 +#define RDA1846_INT_TXON_RF_TO 0x0002 +#define RDA1846_INT_VOX 0x0001 + + +// tx voice channel +#define RDA1846_TX_VOICE_MIC 0x0958 +#define RDA1846_TX_VOICE_TONE2 0x4958 +#define RDA1846_TX_VOICE_GPIO1 0x8958 +#define RDA1846_TX_VOICE_NONE 0xC958 + + +// DTMF ctl +#define RDA1846_DTMF_SINGLE 0x0200 +#define RDA1846_DTMF_DUAL 0x0000 +#define RDA1846_DTMF_EN 0x0100 + +// DTMF tone freq +#include <math.h> + +#define dtmf_tone_freq_hz(value) (uint16_t)round(value/4.096) +#define dtmf_tone_freq_value(hz) (uint16_t)round(hz*4.096) + +#ifdef RDA_QUARTZ_12M288 +// DTMF frequencies @ 12.288 MHz - these are the defaults... are they? +#define RDA1846_DTMF_C0 0x61 // 697 Hz +#define RDA1846_DTMF_C1 0x5B // 770 Hz +#define RDA1846_DTMF_C2 0x53 // 852 Hz +#define RDA1846_DTMF_C3 0x4B // 941 Hz +#define RDA1846_DTMF_C4 0x2C // 1209 Hz +#define RDA1846_DTMF_C5 0x1E // 1336 Hz +#define RDA1846_DTMF_C6 0x0A // 1477 Hz +#define RDA1846_DTMF_C7 0xF6 // 1633 Hz +#endif // RDA_QUARTZ_12M8 + +#ifdef RDA_QUARTZ_13M +// DTMF frequencies @ 13 MHz - these are the defaults... +#define RDA1846_DTMF_C0 0x61 // 697 Hz +#define RDA1846_DTMF_C1 0x5E // 770 Hz +#define RDA1846_DTMF_C2 0x57 // 852 Hz +#define RDA1846_DTMF_C3 0x4B // 941 Hz +#define RDA1846_DTMF_C4 0x31 // 1209 Hz +#define RDA1846_DTMF_C5 0x1E // 1336 Hz +#define RDA1846_DTMF_C6 0x0F // 1477 Hz +#define RDA1846_DTMF_C7 0xFB // 1633 Hz +#endif // RDA_QUARTZ_13M + +#endif |