diff options
Diffstat (limited to 'software/avr.lib/cc1101_defines.h')
| -rw-r--r-- | software/avr.lib/cc1101_defines.h | 153 |
1 files changed, 153 insertions, 0 deletions
diff --git a/software/avr.lib/cc1101_defines.h b/software/avr.lib/cc1101_defines.h new file mode 100644 index 0000000..e9e2e67 --- /dev/null +++ b/software/avr.lib/cc1101_defines.h @@ -0,0 +1,153 @@ +/* + * spreadspace avr utils + * + * + * Copyright (C) 2013-2015 Christian Pointner <equinox@spreadspace.org> + * + * This file is part of spreadspace avr utils. + * + * spreadspace avr utils is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * spreadspace avr utils is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with spreadspace avr utils. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SPREADAVR_CC1101_defines_h_INCLUDED +#define SPREADAVR_CC1101_defines_h_INCLUDED + +//// header byte +#define CC1101_HEADER_READ 0x80 +#define CC1101_HEADER_WRITE 0x00 +#define CC1101_HEADER_BURST 0x40 +#define CC1101_HEADER_READONLY 0xC0 +#define CC1101_HEADER_COMMAND 0x00 + +//read/write config registers: +#define CC1101_REG_RW_IOCFG2 0x00 +#define CC1101_REG_RW_IOCFG1 0x01 +#define CC1101_REG_RW_IOCFG0 0x02 +#define CC1101_REG_RW_FIFOTHR 0x03 +#define CC1101_REG_RW_SYNC1 0x04 +#define CC1101_REG_RW_SYNC0 0x05 +#define CC1101_REG_RW_PKTLEN 0x06 +#define CC1101_REG_RW_PKTCTRL1 0x07 +#define CC1101_REG_RW_PKTCTRL0 0x08 +#define CC1101_REG_RW_ADDR 0x09 +#define CC1101_REG_RW_CHANNR 0x0A +#define CC1101_REG_RW_FSCTRL1 0x0B +#define CC1101_REG_RW_FSCTRL0 0x0C +#define CC1101_REG_RW_FREQ2 0x0D +#define CC1101_REG_RW_FREQ1 0x0E +#define CC1101_REG_RW_FREQ0 0x0F +#define CC1101_REG_RW_MDMCFG4 0x10 +#define CC1101_REG_RW_MDMCFG3 0x11 +#define CC1101_REG_RW_MDMCFG2 0x12 +#define CC1101_REG_RW_MDMCFG1 0x13 +#define CC1101_REG_RW_MDMCFG0 0x14 +#define CC1101_REG_RW_DEVIATN 0x15 +#define CC1101_REG_RW_MCSM2 0x16 +#define CC1101_REG_RW_MCSM1 0x17 +#define CC1101_REG_RW_MCSM0 0x18 +#define CC1101_REG_RW_FOCCFG 0x19 +#define CC1101_REG_RW_BSCFG 0x1A +#define CC1101_REG_RW_AGCCTRL2 0x1B +#define CC1101_REG_RW_AGCCTRL1 0x1C +#define CC1101_REG_RW_AGCCTRL0 0x1D +#define CC1101_REG_RW_WOREVT1 0x1E +#define CC1101_REG_RW_WOREVT0 0x1F +#define CC1101_REG_RW_WORCTRL 0x20 +#define CC1101_REG_RW_FREND1 0x21 +#define CC1101_REG_RW_FREND0 0x22 +#define CC1101_REG_RW_FSCAL3 0x23 +#define CC1101_REG_RW_FSCAL2 0x24 +#define CC1101_REG_RW_FSCAL1 0x25 +#define CC1101_REG_RW_FSCAL0 0x26 +#define CC1101_REG_RW_RCCTRL1 0x27 +#define CC1101_REG_RW_RCCTRL0 0x28 +#define CC1101_REG_RW_FSTEST 0x29 +#define CC1101_REG_RW_PTEST 0x2A +#define CC1101_REG_RW_AGCTEST 0x2B +#define CC1101_REG_RW_TEST2 0x2C +#define CC1101_REG_RW_TEST1 0x2D +#define CC1101_REG_RW_TEST0 0x2E + +#define CC1101_REG_RW_MAX 0x2E + +//read-only status registers: +#define CC1101_REG_RO_PARTNUM 0x30 +#define CC1101_REG_RO_VERSION 0x31 +#define CC1101_REG_RO_FREQUEST 0x32 +#define CC1101_REG_RO_LQI 0x33 +#define CC1101_REG_RO_RSSI 0x34 +#define CC1101_REG_RO_MARCSTATE 0x35 +#define CC1101_REG_RO_WORTIME1 0x36 +#define CC1101_REG_RO_WORTIME0 0x37 +#define CC1101_REG_RO_PKTSTATUS 0x38 +#define CC1101_REG_RO_VCO_VC_DAC 0x39 +#define CC1101_REG_RO_TXBYTES 0x3A +#define CC1101_REG_RO_RXBYTES 0x3B +#define CC1101_REG_RO_RCCTRL1_STATUS 0x3C +#define CC1101_REG_RO_RCCTRL0_STATUS 0x3D + +#define CC1101_REG_RO_MIN 0x30 +#define CC1101_REG_RO_MAX 0x3D + +//commands: +#define CC1101_CMD_SRES 0x30 +#define CC1101_CMD_SFSTXON 0x31 +#define CC1101_CMD_SXOFF 0x32 +#define CC1101_CMD_SCAL 0x33 +#define CC1101_CMD_SRX 0x34 +#define CC1101_CMD_STX 0x35 +#define CC1101_CMD_SIDLE 0x36 +#define CC1101_CMD_SWOR 0x38 +#define CC1101_CMD_SPWD 0x39 +#define CC1101_CMD_SFRX 0x3A +#define CC1101_CMD_SFTX 0x3B +#define CC1101_CMD_SWORRST 0x3C +#define CC1101_CMD_SNOP 0x3D + +#define CC1101_CMD_MIN 0x30 +#define CC1101_CMD_MAX 0x3D + +//power amplifier table +#define CC1101_REG_PATABLE 0x3E +//data FIFOs +#define CC1101_REG_FIFO 0x3F + + +#define CC1101_ADDR_MAX 0x3F + + + +////status byte: +#define CC1101_STATUS_CHIP_NOT_RDY(x) (x & 0b10000000) +#define CC1101_STATUS_IDLE(x) ((x & 0b01110000) == 0b00000000) +#define CC1101_STATUS_RXMODE(x) ((x & 0b01110000) == 0b00010000) +#define CC1101_STATUS_TXMODE(x) ((x & 0b01110000) == 0b00100000) +#define CC1101_STATUS_FSTXON(x) ((x & 0b01110000) == 0b00110000) +#define CC1101_STATUS_CALIBRATE(x) ((x & 0b01110000) == 0b01000000) +#define CC1101_STATUS_SETTLING(x) ((x & 0b01110000) == 0b01010000) +#define CC1101_STATUS_RXFIFO_OVERFLOW(x) ((x & 0b01110000) == 0b01100000) +#define CC1101_STATUS_TXFIFO_OVERFLOW(x) ((x & 0b01110000) == 0b01110000) +#define CC1101_STATUS_FIFO_BYTES_AVAILABLE(x) (x & 0b00001111) + + +#define CC1101_FIFO_MAX_LEN 64 + +//freq Fosc/65536 +#ifdef CC1101_QUARTZ_26M +#define CC1101_FREQ_CORR 396.728515 // = 26000000/65536 +#else +#error Please set Quartz Frequency using the variable: CC1101_QUARTZ_* +#endif // CC1101_QUARTZ_26M + +#endif |