diff options
Diffstat (limited to 'contrib/CMSISv1p30_LPC13xx')
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/.cproject | 891 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/.project | 81 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/cmsis_readme.txt | 28 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/docs/CMSIS changes.htm | 320 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/docs/CMSIS debug support.htm | 243 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/docs/CMSIS_Core.htm | 1337 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/docs/License.doc | bin | 39936 -> 0 bytes | |||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/history.txt | 12 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/inc/LPC13xx.h | 493 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/inc/core_cm3.h | 1818 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/inc/system_LPC13xx.h | 64 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/src/core_cm3.c | 784 | ||||
| -rw-r--r-- | contrib/CMSISv1p30_LPC13xx/src/system_LPC13xx.c | 487 |
13 files changed, 0 insertions, 6558 deletions
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-<peripheralInstance derived_from="LPC11_13_WDT" determined="infoFile" id="WDT" location="0x40004000"/>
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-<processor>
-<name gcc_name="cortex-m3">Cortex-M3</name>
-<family>Cortex-M</family>
-</processor>
-<link href="nxp_lpc11_13_peripheral.xme" show="embed" type="simple"/>
-</info>
-</infoList>
-</TargetConfig></projectStorage>
-</storageModule>
-</cproject>
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-<projectDescription>
- <name>CMSISv1p30_LPC13xx</name>
- <comment></comment>
- <projects>
- </projects>
- <buildSpec>
- <buildCommand>
- <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
- <triggers>clean,full,incremental,</triggers>
- <arguments>
- <dictionary>
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- <value></value>
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- <value>make</value>
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diff --git a/contrib/CMSISv1p30_LPC13xx/cmsis_readme.txt b/contrib/CMSISv1p30_LPC13xx/cmsis_readme.txt deleted file mode 100644 index 2ce3bc2..0000000 --- a/contrib/CMSISv1p30_LPC13xx/cmsis_readme.txt +++ /dev/null @@ -1,28 +0,0 @@ -CMSIS : Cortex Microcontroller Software Interface Standard
-==========================================================
-CMSIS defines for a Cortex-M Microcontroller System:
-
- * A common way to access peripheral registers and a
- common way to define exception vectors.
- * The register names of the Core Peripherals and the
- names of the Core Exception Vectors.
- * An device independent interface for RTOS Kernels
- including a debug channel.
-
-By using CMSIS compliant software components, the user can
-easier re-use template code. CMSIS is intended to enable the
-combination of software components from multiple middleware
-vendors.
-
-This project contains appropriate files for this MCU family
-taken from CMSIS. A full copy of the CMSIS files can be found
-within your tools installation directory. More information on
-CMSIS can be found at:
-
- http://www.onarm.com/
- http://www.arm.com/
-
-
-
-
-
diff --git a/contrib/CMSISv1p30_LPC13xx/docs/CMSIS changes.htm b/contrib/CMSISv1p30_LPC13xx/docs/CMSIS changes.htm deleted file mode 100644 index 162ffcc..0000000 --- a/contrib/CMSISv1p30_LPC13xx/docs/CMSIS changes.htm +++ /dev/null @@ -1,320 +0,0 @@ -<html>
-
-<head>
-<title>CMSIS Changes</title>
-<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
-<meta name="ProgId" content="FrontPage.Editor.Document">
-<style>
-<!--
-/*-----------------------------------------------------------
-Keil Software CHM Style Sheet
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-h1 { font-family: Verdana; font-size: 18pt; color: #000080; font-weight: bold;
- text-align: Center; margin-right: 3 }
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- background-color: #CCCCCC; margin-top: 24; margin-bottom: 3;
- padding: 6 }
-h3 { font-family: Verdana; font-size: 10pt; font-weight: bold; background-color:
- #CCCCCC; margin-top: 24; margin-bottom: 3; padding: 6 }
-pre { font-family: Courier New; font-size: 10pt; background-color: #CCFFCC;
- margin-left: 24; margin-right: 24 }
-ul { list-style-type: square; margin-top: 6pt; margin-bottom: 0 }
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-tr { text-align: left; vertical-align: top }
-td { text-align: left; vertical-align: top; padding-right: 6pt }
-.ToolT { font-size: 8pt; color: #808080 }
-.TinyT { font-size: 8pt; text-align: Center }
-code { color: #000000; background-color: #E0E0E0; font-family: 'Courier New', Courier;
- line-height: 120%; font-style: normal }
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-img.expand { border-style: none; border-width: medium }
-div.expand { display: none; margin-left: 9pt; margin-top: 0 }
-/*-----------------------------------------------------------
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-p.wh { font-weight: bold; clear: both; margin-top: 6pt; margin-bottom: 3pt }
-table.wh { width: 100% }
-td.whItem { white-space: nowrap; font-style: italic; padding-right: 6pt; padding-bottom:
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-td.kt { color: #000000; background-color: #E0E0E0; border-top: 1pt solid #A0A0A0;
- padding-left: 6pt; padding-right: 6pt; padding-top: 2pt;
- padding-bottom: 2pt }
-/*-----------------------------------------------------------
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--->
-
-</style>
-</head>
-
-<body>
-
-<h1>Changes to CMSIS version V1.20</h1>
-
-<hr>
-
-<h2>1. Removed CMSIS Middelware packages</h2>
-<p>
- CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found.
-</p>
-
-<h2>2. SystemFrequency renamed to SystemCoreClock</h2>
-<p>
- The variable name <strong>SystemCoreClock</strong> is more precise than <strong>SystemFrequency</strong>
- because the variable holds the clock value at which the core is running.
-</p>
-
-<h2>3. Changed startup concept</h2>
-<p>
- The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit
- from main) has the weakness that it does not work for controllers which need a already
- configuerd clock system to configure the external memory controller.
-</p>
-
-<h3>Changed startup concept</h3>
-<ul>
- <li>
- SystemInit() is called from startup file before <strong>premain</strong>.
- </li>
- <li>
- <strong>SystemInit()</strong> configures the clock system and also configures
- an existing external memory controller.
- </li>
- <li>
- <strong>SystemInit()</strong> must not use global variables.
- </li>
- <li>
- <strong>SystemCoreClock</strong> is initialized with a correct predefined value.
- </li>
- <li>
- Additional function <strong>void SystemCoreClockUpdate (void)</strong> is provided.<br>
- <strong>SystemCoreClockUpdate()</strong> updates the variable <strong>SystemCoreClock</strong>
- and must be called whenever the core clock is changed.<br>
- <strong>SystemCoreClockUpdate()</strong> evaluates the clock register settings and calculates
- the current core clock.
- </li>
-</ul>
-
-
-<h2>4. Advanced Debug Functions</h2>
-<p>
- ITM communication channel is only capable for OUT direction. To allow also communication for
- IN direction a simple concept is provided.
-</p>
-<ul>
- <li>
- Global variable <strong>volatile int ITM_RxBuffer</strong> used for IN data.
- </li>
- <li>
- Function <strong>int ITM_CheckChar (void)</strong> checks if a new character is available.
- </li>
- <li>
- Function <strong>int ITM_ReceiveChar (void)</strong> retrieves the new character.
- </li>
-</ul>
-
-<p>
- For detailed explanation see file <strong>CMSIS debug support.htm</strong>.
-</p>
-
-
-<h2>5. Core Register Bit Definitions</h2>
-<p>
- Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the
- defines correspond with the Cortex-M Technical Reference Manual.
-</p>
-<p>
- e.g. SysTick structure with bit definitions
-</p>
-<pre>
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
- @{
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */</pre>
-
-<h2>7. DoxyGen Tags</h2>
-<p>
- DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation
- using DoxyGen.
-</p>
-
-<h2>8. Folder Structure</h2>
-<p>
- The folder structure is changed to differentiate the single support packages.
-</p>
-
- <ul>
- <li>CM0</li>
- <li>CM3
- <ul>
- <li>CoreSupport</li>
- <li>DeviceSupport</li>
- <ul>
- <li>Vendor
- <ul>
- <li>Device
- <ul>
- <li>Startup
- <ul>
- <li>Toolchain</li>
- <li>Toolchain</li>
- <li>...</li>
- </ul>
- </li>
- </ul>
- </li>
- <li>Device</li>
- <li>...</li>
- </ul>
- </li>
- <li>Vendor</li>
- <li>...</li>
- </ul>
- </li>
- <li>Example
- <ul>
- <li>Toolchain
- <ul>
- <li>Device</li>
- <li>Device</li>
- <li>...</li>
- </ul>
- </li>
- <li>Toolchain</li>
- <li>...</li>
- </ul>
- </li>
- </ul>
- </li>
-
- <li>Documentation</li>
- </ul>
-
-<h2>9. Open Points</h2>
-<p>
- Following points need to be clarified and solved:
-</p>
-<ul>
- <li>
- <p>
- Equivalent C and Assembler startup files.
- </p>
- <p>
- Is there a need for having C startup files although assembler startup files are
- very efficient and do not need to be changed?
- <p/>
- </li>
- <li>
- <p>
- Placing of HEAP in external RAM.
- </p>
- <p>
- It must be possible to place HEAP in external RAM if the device supports an
- external memory controller.
- </p>
- </li>
- <li>
- <p>
- Placing of STACK /HEAP.
- </p>
- <p>
- STACK should always be placed at the end of internal RAM.
- </p>
- <p>
- If HEAP is placed in internal RAM than it should be placed after RW ZI section.
- </p>
- </li>
- <li>
- <p>
- Removing core_cm3.c and core_cm0.c.
- </p>
- <p>
- On a long term the functions in core_cm3.c and core_cm0.c must be replaced with
- appropriate compiler intrinsics.
- </p>
- </li>
-</ul>
-
-
-<h2>10. Limitations</h2>
-<p>
- The following limitations are not covered with the current CMSIS version:
-</p>
-<ul>
- <li>
- No <strong>C startup files</strong> for ARM toolchain are provided.
- </li>
- <li>
- No <strong>C startup files</strong> for GNU toolchain are provided.
- </li>
- <li>
- No <strong>C startup files</strong> for IAR toolchain are provided.
- </li>
- <li>
- No <strong>Tasking</strong> projects are provided yet.
- </li>
-</ul>
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-
-<head>
-<title>CMSIS Debug Support</title>
-<meta http-equiv="Content-Type" content="text/html; charset=windows-1252">
-<meta name="GENERATOR" content="Microsoft FrontPage 6.0">
-<meta name="ProgId" content="FrontPage.Editor.Document">
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-/*-----------------------------------------------------------
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--->
-
-</style>
-</head>
-
-<body>
-
-<h1>CMSIS Debug Support</h1>
-
-<hr>
-
-<h2>Cortex-M3 ITM Debug Access</h2>
-<p>
- The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with
- the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has
- 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM
- communication channels are used by CMSIS to output the following information:
-</p>
-<ul>
- <li>ITM Channel 0: used for printf-style output via the debug interface.</li>
- <li>ITM Channel 31: is reserved for RTOS kernel awareness debugging.</li>
-</ul>
-
-<h2>Debug IN / OUT functions</h2>
-<p>CMSIS provides following debug functions:</p>
-<ul>
- <li>ITM_SendChar (uses ITM channel 0)</li>
- <li>ITM_ReceiveChar (uses global variable)</li>
- <li>ITM_CheckChar (uses global variable)</li>
-</ul>
-
-<h3>ITM_SendChar</h3>
-<p>
- <strong>ITM_SendChar</strong> is used to transmit a character over ITM channel 0 from
- the microcontroller system to the debug system. <br>
- Only a 8 bit value is transmitted.
-</p>
-<pre>
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- /* check if debugger connected and ITM channel enabled for tracing */
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
- (ITM->TCR & ITM_TCR_ITMENA) &&
- (ITM->TER & (1UL << 0)) )
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t)ch;
- }
- return (ch);
-}</pre>
-
-<h3>ITM_ReceiveChar</h3>
-<p>
- ITM communication channel is only capable for OUT direction. For IN direction
- a globel variable is used. A simple mechansim detects if a character is received.
- The project to test need to be build with debug information.
-</p>
-
-<p>
- The globale variable <strong>ITM_RxBuffer</strong> is used to transmit a 8 bit value from debug system
- to microcontroller system. <strong>ITM_RxBuffer</strong> is 32 bit wide to enshure a proper handshake.
-</p>
-<pre>
-extern volatile int ITM_RxBuffer; /* variable to receive characters */
-</pre>
-<p>
- A dedicated bit pattern is used to determin if <strong>ITM_RxBuffer</strong> is empty
- or contains a valid value.
-</p>
-<pre>
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
-</pre>
-<p>
- <strong>ITM_ReceiveChar</strong> is used to receive a 8 bit value from the debug system. The function is nonblocking.
- It returns the received character or '-1' if no character was available.
-</p>
-<pre>
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-</pre>
-
-<h3>ITM_CheckChar</h3>
-<p>
- <strong>ITM_CheckChar</strong> is used to check if a character is received.
-</p>
-<pre>
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}</pre>
-
-
-<h2>ITM Debug Support in uVision</h2>
-<p>
- uVision uses in a debug session the <strong>Debug (printf) Viewer</strong> window to
- display the debug data.
-</p>
-<p>Direction microcontroller system -> uVision:</p>
-<ul>
- <li>
- Characters received via ITM communication channel 0 are written in a printf style
- to <strong>Debug (printf) Viewer</strong> window.
- </li>
-</ul>
-
-<p>Direction uVision -> microcontroller system:</p>
-<ul>
- <li>Check if <strong>ITM_RxBuffer</strong> variable is available (only performed once).</li>
- <li>Read character from <strong>Debug (printf) Viewer</strong> window.</li>
- <li>If <strong>ITM_RxBuffer</strong> empty write character to <strong>ITM_RxBuffer</strong>.</li>
-</ul>
-
-<p class="Note">Note</p>
-<ul>
- <li><p>Current solution does not use a buffer machanism for trasmitting the characters.</p>
- </li>
-</ul>
-
-<h2>RTX Kernel awareness in uVision</h2>
-<p>
- uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
- No format overhead is necessary.<br>
- uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
- to ITM communication channel 31.
-</p>
-
-<p>Following RTX events are traced:</p>
-<ul>
- <li>Task Create / Delete event
- <ol>
- <li>32 bit access. Task start address is transmitted</li>
- <li>16 bit access. Task ID and Create/Delete flag are transmitted<br>
- High byte holds Create/Delete flag, Low byte holds TASK ID.
- </li>
- </ol>
- </li>
- <li>Task switch event
- <ol>
- <li>8 bit access. Task ID of current task is transmitted</li>
- </ol>
- </li>
-</ul>
-
-<p class="Note">Note</p>
-<ul>
- <li><p>Other RTOS information could be retrieved via memory read access in a polling mode manner.</p>
- </li>
-</ul>
-
-
-<p class="MsoNormal"><span lang="EN-GB"> </span></p>
-
-<hr>
-
-<p class="TinyT">Copyright © KEIL - An ARM Company.<br>
-All rights reserved.<br>
-Visit our web site at <a href="http://www.keil.com">www.keil.com</a>.
-</p>
-
-</body>
-
-</html>
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-}
-.O
- {color:#1D315B;
- font-size:149%;}
- -->
- </style></head>
-<body>
-<h1>Cortex Microcontroller Software Interface Standard</h1>
-
-<p align="center">This file describes the Cortex Microcontroller Software Interface Standard (CMSIS).</p>
-<p align="center">Version: 1.30 - 30. October 2009</p>
-
-<p class="TinyT">Information in this file, the accompany manuals, and software is<br>
- Copyright © ARM Ltd.<br>All rights reserved.
-</p>
-
-<hr>
-
-<p><span style="FONT-WEIGHT: bold">Revision History</span></p>
-<ul>
- <li>Version 1.00: initial release. </li>
- <li>Version 1.01: added __LDREX<em>x</em>, __STREX<em>x</em>, and __CLREX.</li>
- <li>Version 1.02: added Cortex-M0. </li>
- <li>Version 1.10: second review. </li>
- <li>Version 1.20: third review. </li>
- <li>Version 1.30 PRE-RELEASE: reworked Startup Concept, additional Debug Functionality.</li>
- <li>Version 1.30 2nd PRE-RELEASE: changed folder structure, added doxyGen comments, added Bit definitions.</li>
- <li>Version 1.30: updated Device Support Packages.</li>
-</ul>
-
-<hr>
-
-<h2>Contents</h2>
-
-<ol>
- <li class="LI2"><a href="#1">About</a></li>
- <li class="LI2"><a href="#2">Coding Rules and Conventions</a></li>
- <li class="LI2"><a href="#3">CMSIS Files</a></li>
- <li class="LI2"><a href="#4">Core Peripheral Access Layer</a></li>
- <li class="LI2"><a href="#5">CMSIS Example</a></li>
-</ol>
-
-<h2><a name="1"></a>About</h2>
-
-<p>
- The <strong>Cortex Microcontroller Software Interface Standard (CMSIS)</strong> answers the challenges
- that are faced when software components are deployed to physical microcontroller devices based on a
- Cortex-M0 or Cortex-M3 processor. The CMSIS will be also expanded to future Cortex-M
- processor cores (the term Cortex-M is used to indicate that). The CMSIS is defined in close co-operation
- with various silicon and software vendors and provides a common approach to interface to peripherals,
- real-time operating systems, and middleware components.
-</p>
-
-<p>ARM provides as part of the CMSIS the following software layers that are
-available for various compiler implementations:</p>
-<ul>
- <li><strong>Core Peripheral Access Layer</strong>: contains name definitions,
- address definitions and helper functions to
- access core registers and peripherals. It defines also a device
- independent interface for RTOS Kernels that includes debug channel
- definitions.</li>
-</ul>
-
-<p>These software layers are expanded by Silicon partners with:</p>
-<ul>
- <li><strong>Device Peripheral Access Layer</strong>: provides definitions
- for all device peripherals</li>
- <li><strong>Access Functions for Peripherals (optional)</strong>: provides
- additional helper functions for peripherals</li>
-</ul>
-
-<p>CMSIS defines for a Cortex-M Microcontroller System:</p>
-<ul>
- <li style="text-align: left;">A common way to access peripheral registers
- and a common way to define exception vectors.</li>
- <li style="text-align: left;">The register names of the <strong>Core
- Peripherals</strong> and<strong> </strong>the names of the <strong>Core
- Exception Vectors</strong>.</li>
- <li>An device independent interface for RTOS Kernels including a debug
- channel.</li>
-</ul>
-
-<p>
- By using CMSIS compliant software components, the user can easier re-use template code.
- CMSIS is intended to enable the combination of software components from multiple middleware vendors.
-</p>
-
-<h2><a name="2"></a>Coding Rules and Conventions</h2>
-
-<p>
- The following section describes the coding rules and conventions used in the CMSIS
- implementation. It contains also information about data types and version number information.
-</p>
-
-<h3>Essentials</h3>
-<ul>
- <li>The CMSIS C code conforms to MISRA 2004 rules. In case of MISRA violations,
- there are disable and enable sequences for PC-LINT inserted.</li>
- <li>ANSI standard data types defined in the ANSI C header file
- <strong><stdint.h></strong> are used.</li>
- <li>#define constants that include expressions must be enclosed by
- parenthesis.</li>
- <li>Variables and parameters have a complete data type.</li>
- <li>All functions in the <strong>Core Peripheral Access Layer</strong> are
- re-entrant.</li>
- <li>The <strong>Core Peripheral Access Layer</strong> has no blocking code
- (which means that wait/query loops are done at other software layers).</li>
- <li>For each exception/interrupt there is definition for:
- <ul>
- <li>an exception/interrupt handler with the postfix <strong>_Handler </strong>
- (for exceptions) or <strong>_IRQHandler</strong> (for interrupts).</li>
- <li>a default exception/interrupt handler (weak definition) that contains an endless loop.</li>
- <li>a #define of the interrupt number with the postfix <strong>_IRQn</strong>.</li>
- </ul></li>
-</ul>
-
-<h3>Recommendations</h3>
-
-<p>The CMSIS recommends the following conventions for identifiers.</p>
-<ul>
- <li><strong>CAPITAL</strong> names to identify Core Registers, Peripheral Registers, and CPU Instructions.</li>
- <li><strong>CamelCase</strong> names to identify peripherals access functions and interrupts.</li>
- <li><strong>PERIPHERAL_</strong> prefix to identify functions that belong to specify peripherals.</li>
- <li><strong>Doxygen</strong> comments for all functions are included as described under <strong>Function Comments</strong> below.</li>
-</ul>
-
-<b>Comments</b>
-
-<ul>
- <li>Comments use the ANSI C90 style (<em>/* comment */</em>) or C++ style
- (<em>// comment</em>). It is assumed that the programming tools support today
- consistently the C++ comment style.</li>
- <li><strong>Function Comments</strong> provide for each function the following information:
- <ul>
- <li>one-line brief function overview.</li>
- <li>detailed parameter explanation.</li>
- <li>detailed information about return values.</li>
- <li>detailed description of the actual function.</li>
- </ul>
- <p><b>Doxygen Example:</b></p>
- <pre>
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- * @param IRQn interrupt number that specifies the interrupt
- * @return none.
- * Enable the specified interrupt in the NVIC Interrupt Controller.
- * Other settings of the interrupt such as priority are not affected.
- */</pre>
- </li>
-</ul>
-
-<h3>Data Types and IO Type Qualifiers</h3>
-
-<p>
- The <strong>Cortex-M HAL</strong> uses the standard types from the standard ANSI C header file
- <strong><stdint.h></strong>. <strong>IO Type Qualifiers</strong> are used to specify the access
- to peripheral variables. IO Type Qualifiers are indented to be used for automatic generation of
- debug information of peripheral registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">IO Type Qualifier</th>
- <th class="kt">#define</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__I</td>
- <td class="kt">volatile const</td>
- <td class="kt">Read access only</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__O</td>
- <td class="kt">volatile</td>
- <td class="kt">Write access only</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__IO</td>
- <td class="kt">volatile</td>
- <td class="kt">Read and write access</td>
- </tr>
- </tbody>
-</table>
-
-<h3>CMSIS Version Number</h3>
-<p>
- File <strong>core_cm3.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)</pre>
-
-<p>
- File <strong>core_cm0.h</strong> contains the version number of the CMSIS with the following define:
-</p>
-
-<pre>
-#define __CM0_CMSIS_VERSION_MAIN (0x01) /* [31:16] main version */
-#define __CM0_CMSIS_VERSION_SUB (0x30) /* [15:0] sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB)</pre>
-
-
-<h3>CMSIS Cortex Core</h3>
-<p>
- File <strong>core_cm3.h</strong> contains the type of the CMSIS Cortex-M with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M (0x03)</pre>
-
-<p>
- File <strong>core_cm0.h</strong> contains the type of the CMSIS Cortex-M with the following define:
-</p>
-
-<pre>
-#define __CORTEX_M (0x00)</pre>
-
-
-<h2><a name="3"></a>CMSIS Files</h2>
-<p>
- This section describes the Files provided in context with the CMSIS to access the Cortex-M
- hardware and peripherals.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">File</th>
- <th class="kt">Provider</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap"><i>device.h</i></td>
- <td class="kt">Device specific (provided by silicon partner)</td>
- <td class="kt">Defines the peripherals for the actual device. The file may use
- several other include files to define the peripherals of the actual device.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm0.h</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Defines the core peripherals for the Cortex-M0 CPU and core peripherals.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm3.h</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Defines the core peripherals for the Cortex-M3 CPU and core peripherals.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm0.c</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Provides helper functions that access core registers.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">core_cm3.c</td>
- <td class="kt">ARM (for RealView ARMCC, IAR, and GNU GCC)</td>
- <td class="kt">Provides helper functions that access core registers.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">startup<i>_device</i></td>
- <td class="kt">ARM (adapted by compiler partner / silicon partner)</td>
- <td class="kt">Provides the Cortex-M startup code and the complete (device specific) Interrupt Vector Table</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">system<i>_device</i></td>
- <td class="kt">ARM (adapted by silicon partner)</td>
- <td class="kt">Provides a device specific configuration file for the device. It configures the device initializes
- typically the oscillator (PLL) that is part of the microcontroller device</td>
- </tr>
- </tbody>
-</table>
-
-<h3><em>device.h</em></h3>
-
-<p>
- The file <em><strong>device.h</strong></em> is provided by the silicon vendor and is the
- <u><strong>central include file</strong></u> that the application programmer is using in
- the C source code. This file contains:
-</p>
-<ul>
- <li>
- <p><strong>Interrupt Number Definition</strong>: provides interrupt numbers
- (IRQn) for all core and device specific exceptions and interrupts.</p>
- </li>
- <li>
- <p><strong>Configuration for core_cm0.h / core_cm3.h</strong>: reflects the
- actual configuration of the Cortex-M processor that is part of the actual
- device. As such the file <strong>core_cm0.h / core_cm3.h</strong> is included that
- implements access to processor registers and core peripherals. </p>
- </li>
- <li>
- <p><strong>Device Peripheral Access Layer</strong>: provides definitions
- for all device peripherals. It contains all data structures and the address
- mapping for the device specific peripherals. </p>
- </li>
- <li><strong>Access Functions for Peripherals (optional)</strong>: provides
- additional helper functions for peripherals that are useful for programming
- of these peripherals. Access Functions may be provided as inline functions
- or can be extern references to a device specific library provided by the
- silicon vendor.</li>
-</ul>
-
-
-<h4><strong>Interrupt Number Definition</strong></h4>
-
-<p>To access the device specific interrupts the device.h file defines IRQn
-numbers for the complete device using a enum typedef as shown below:</p>
-<pre>
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions/Interrupt Numbers ************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-/****** STM32 specific Interrupt Numbers ****************************************************************/
- WWDG_STM_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_STM_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
- :
- :
- } IRQn_Type;</pre>
-
-
-<h4>Configuration for core_cm0.h / core_cm3.h</h4>
-<p>
- The Cortex-M core configuration options which are defined for each device implementation. Some
- configuration options are reflected in the CMSIS layer using the #define settings described below.
-</p>
-<p>
- To access core peripherals file <em><strong>device.h</strong></em> includes file <b>core_cm0.h / core_cm3.h</b>.
- Several features in <strong>core_cm0.h / core_cm3.h</strong> are configured by the following defines that must be
- defined before <strong>#include <core_cm0.h></strong> / <strong>#include <core_cm3.h></strong>
- preprocessor command.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">#define</th>
- <th class="kt" nowrap="nowrap">File</th>
- <th class="kt" nowrap="nowrap">Value</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
- <td class="kt">core_cm0.h</td>
- <td class="kt" nowrap="nowrap">(2)</td>
- <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__NVIC_PRIO_BITS</td>
- <td class="kt">core_cm3.h</td>
- <td class="kt" nowrap="nowrap">(2 ... 8)</td>
- <td class="kt">Number of priority bits implemented in the NVIC (device specific)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__MPU_PRESENT</td>
- <td class="kt">core_cm0.h, core_cm3.h</td>
- <td class="kt" nowrap="nowrap">(0, 1)</td>
- <td class="kt">Defines if an MPU is present or not</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">__Vendor_SysTickConfig</td>
- <td class="kt">core_cm0.h, core_cm3.h</td>
- <td class="kt" nowrap="nowrap">(1)</td>
- <td class="kt">When this define is setup to 1, the <strong>SysTickConfig</strong> function
- in <strong>core_cm3.h</strong> is excluded. In this case the <em><strong>device.h</strong></em>
- file must contain a vendor specific implementation of this function.</td>
- </tr>
- </tbody>
-</table>
-
-
-<h4>Device Peripheral Access Layer</h4>
-<p>
- Each peripheral uses a prefix which consists of <strong><device abbreviation>_</strong>
- and <strong><peripheral name>_</strong> to identify peripheral registers that access this
- specific peripheral. The intention of this is to avoid name collisions caused
- due to short names. If more than one peripheral of the same type exists,
- identifiers have a postfix (digit or letter). For example:
-</p>
-<ul>
- <li><device abbreviation>_UART_Type: defines the generic register layout for all UART channels in a device.
- <pre>
-typedef struct
-{
- union {
- __I uint8_t RBR; /*!< Offset: 0x000 Receiver Buffer Register */
- __O uint8_t THR; /*!< Offset: 0x000 Transmit Holding Register */
- __IO uint8_t DLL; /*!< Offset: 0x000 Divisor Latch LSB */
- uint32_t RESERVED0;
- };
- union {
- __IO uint8_t DLM; /*!< Offset: 0x004 Divisor Latch MSB */
- __IO uint32_t IER; /*!< Offset: 0x004 Interrupt Enable Register */
- };
- union {
- __I uint32_t IIR; /*!< Offset: 0x008 Interrupt ID Register */
- __O uint8_t FCR; /*!< Offset: 0x008 FIFO Control Register */
- };
- __IO uint8_t LCR; /*!< Offset: 0x00C Line Control Register */
- uint8_t RESERVED1[7];
- __I uint8_t LSR; /*!< Offset: 0x014 Line Status Register */
- uint8_t RESERVED2[7];
- __IO uint8_t SCR; /*!< Offset: 0x01C Scratch Pad Register */
- uint8_t RESERVED3[3];
- __IO uint32_t ACR; /*!< Offset: 0x020 Autobaud Control Register */
- __IO uint8_t ICR; /*!< Offset: 0x024 IrDA Control Register */
- uint8_t RESERVED4[3];
- __IO uint8_t FDR; /*!< Offset: 0x028 Fractional Divider Register */
- uint8_t RESERVED5[7];
- __IO uint8_t TER; /*!< Offset: 0x030 Transmit Enable Register */
- uint8_t RESERVED6[39];
- __I uint8_t FIFOLVL; /*!< Offset: 0x058 FIFO Level Register */
-} LPC_UART_TypeDef;</pre>
- </li>
- <li><device abbreviation>_UART1: is a pointer to a register structure that refers to a specific UART.
- For example UART1->DR is the data register of UART1.
- <pre>
-#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
-#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )</pre>
- </li>
-</ul>
-
-<h5>Minimal Requiements</h5>
-<p>
- To access the peripheral registers and related function in a device the files <strong><em>device.h</em></strong>
- and <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong> defines as a minimum:
-</p>
-<ul>
- <li>The <strong>Register Layout Typedef</strong> for each peripheral that defines all register names.
- Names that start with RESERVE are used to introduce space into the structure to adjust the addresses of
- the peripheral registers. For example:
- <pre>
-typedef struct {
- __IO uint32_t CTRL; /* SysTick Control and Status Register */
- __IO uint32_t LOAD; /* SysTick Reload Value Register */
- __IO uint32_t VAL; /* SysTick Current Value Register */
- __I uint32_t CALIB; /* SysTick Calibration Register */
- } SysTick_Type;</pre>
- </li>
-
- <li>
- <strong>Base Address</strong> for each peripheral (in case of multiple peripherals
- that use the same <strong>register layout typedef</strong> multiple base addresses are defined). For example:
- <pre>
-#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */</pre>
- </li>
-
- <li>
- <strong>Access Definition</strong> for each peripheral (in case of multiple peripherals that use
- the same <strong>register layout typedef</strong> multiple access definitions exist, i.e. LPC_UART0,
- LPC_UART2). For Example:
- <pre>
-#define SysTick ((SysTick_Type *) SysTick_BASE) /* SysTick access definition */</pre>
- </li>
-</ul>
-
-<p>
- These definitions allow to access the peripheral registers from user code with simple assignments like:
-</p>
-<pre>SysTick->CTRL = 0;</pre>
-
-<h5>Optional Features</h5>
-<p>In addition the <em> <strong>device.h </strong></em>file may define:</p>
-<ul>
- <li>
- #define constants that simplify access to the peripheral registers.
- These constant define bit-positions or other specific patterns are that required for the
- programming of the peripheral registers. The identifiers used start with
- <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>.
- It is recommended to use CAPITAL letters for such #define constants.
- </li>
- <li>
- Functions that perform more complex functions with the peripheral (i.e. status query before
- a sending register is accessed). Again these function start with
- <strong><device abbreviation>_</strong> and <strong><peripheral name>_</strong>.
- </li>
-</ul>
-
-<h3>core_cm0.h and core_cm0.c</h3>
-<p>
- File <b>core_cm0.h</b> describes the data structures for the Cortex-M0 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M0 core registers
- and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>
- File <b>core_cm0.c</b> defines several helper functions that access processor registers.
-</p>
-<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M0.</p>
-
-<h3>core_cm3.h and core_cm3.c</h3>
-<p>
- File <b>core_cm3.h</b> describes the data structures for the Cortex-M3 core peripherals and does
- the address mapping of this structures. It also provides basic access to the Cortex-M3 core registers
- and core peripherals with efficient functions (defined as <strong>static inline</strong>).
-</p>
-<p>
- File <b>core_cm3.c</b> defines several helper functions that access processor registers.
-</p>
-<p>Together these files implement the <a href="#4">Core Peripheral Access Layer</a> for a Cortex-M3.</p>
-
-<h3>startup_<em>device</em></h3>
-<p>
- A template file for <strong>startup_<em>device</em></strong> is provided by ARM for each supported
- compiler. It is adapted by the silicon vendor to include interrupt vectors for all device specific
- interrupt handlers. Each interrupt handler is defined as <strong><em>weak</em></strong> function
- to an dummy handler. Therefore the interrupt handler can be directly used in application software
- without any requirements to adapt the <strong>startup_<em>device</em></strong> file.
-</p>
-<p>
- The following exception names are fixed and define the start of the vector table for a Cortex-M0:
-</p>
-<pre>
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler</pre>
-
-<p>
- The following exception names are fixed and define the start of the vector table for a Cortex-M3:
-</p>
-<pre>
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD MemManage_Handler ; MPU Fault Handler
- DCD BusFault_Handler ; Bus Fault Handler
- DCD UsageFault_Handler ; Usage Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD DebugMon_Handler ; Debug Monitor Handler
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler</pre>
-
-<p>
- In the following examples for device specific interrupts are shown:
-</p>
-<pre>
-; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD TAMPER_IRQHandler ; Tamper</pre>
-
-<p>
- Device specific interrupts must have a dummy function that can be overwritten in user code.
- Below is an example for this dummy function.
-</p>
-<pre>
-Default_Handler PROC
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT TAMPER_IRQHandler [WEAK]
- :
- :
- WWDG_IRQHandler
- PVD_IRQHandler
- TAMPER_IRQHandler
- :
- :
- B .
- ENDP</pre>
-
-<p>
- The user application may simply define an interrupt handler function by using the handler name
- as shown below.
-</p>
-<pre>
-void WWDG_IRQHandler(void)
-{
- :
- :
-}</pre>
-
-
-<h3><a name="4"></a>system_<em>device</em>.c</h3>
-<p>
- A template file for <strong>system_<em>device</em>.c</strong> is provided by ARM but adapted by
- the silicon vendor to match their actual device. As a <strong>minimum requirement</strong>
- this file must provide a device specific system configuration function and a global variable
- that contains the system frequency. It configures the device and initializes typically the
- oscillator (PLL) that is part of the microcontroller device.
-</p>
-<p>
- The file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong> must provide
- as a minimum requirement the SystemInit function as shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Function Definition</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void SystemInit (void)</td>
- <td class="kt">Setup the microcontroller system. Typically this function configures the
- oscillator (PLL) that is part of the microcontroller device. For systems
- with variable clock speed it also updates the variable SystemCoreClock.<br>
- SystemInit is called from startup<i>_device</i> file.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void SystemCoreClockUpdate (void)</td>
- <td class="kt">Updates the variable SystemCoreClock and must be called whenever the
- core clock is changed during program execution. SystemCoreClockUpdate()
- evaluates the clock register settings and calculates the current core clock.
-</td>
- </tr>
- </tbody>
-</table>
-
-<p>
- Also part of the file <strong>system_</strong><em><strong>device</strong></em><strong>.c</strong>
- is the variable <strong>SystemCoreClock</strong> which contains the current CPU clock speed shown below.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Variable Definition</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t SystemCoreClock</td>
- <td class="kt">Contains the system core clock (which is the system clock frequency supplied
- to the SysTick timer and the processor core clock). This variable can be
- used by the user application to setup the SysTick timer or configure other
- parameters. It may also be used by debugger to query the frequency of the
- debug timer or configure the trace clock speed.<br>
- SystemCoreClock is initialized with a correct predefined value.<br><br>
- The compiler must be configured to avoid the removal of this variable in
- case that the application program is not using it. It is important for
- debug systems that the variable is physically present in memory so that
- it can be examined to configure the debugger.</td>
- </tr>
- </tbody>
-</table>
-
-<p class="Note">Note</p>
-<ul>
- <li><p>The above definitions are the minimum requirements for the file <strong>
- system_</strong><em><strong>device</strong></em><strong>.c</strong>. This
- file may export more functions or variables that provide a more flexible
- configuration of the microcontroller system.</p>
- </li>
-</ul>
-
-
-<h2>Core Peripheral Access Layer</h2>
-
-<h3>Cortex-M Core Register Access</h3>
-<p>
- The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>
- and provide access to Cortex-M core registers.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Function Definition</th>
- <th class="kt">Core</th>
- <th class="kt">Core Register</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __enable_irq (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PRIMASK = 0</td>
- <td class="kt">Global Interrupt enable (using the instruction <strong>CPSIE
- i</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __disable_irq (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PRIMASK = 1</td>
- <td class="kt">Global Interrupt disable (using the instruction <strong>
- CPSID i</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_PRIMASK (uint32_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PRIMASK = value</td>
- <td class="kt">Assign value to Priority Mask Register (using the instruction
- <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_PRIMASK (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return PRIMASK</td>
- <td class="kt">Return Priority Mask Register (using the instruction
- <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __enable_fault_irq (void)</td>
- <td class="kt">M3</td>
- <td class="kt">FAULTMASK = 0</td>
- <td class="kt">Global Fault exception and Interrupt enable (using the
- instruction <strong>CPSIE
- f</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __disable_fault_irq (void)</td>
- <td class="kt">M3</td>
- <td class="kt">FAULTMASK = 1</td>
- <td class="kt">Global Fault exception and Interrupt disable (using the
- instruction <strong>CPSID f</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_FAULTMASK (uint32_t value)</td>
- <td class="kt">M3</td>
- <td class="kt">FAULTMASK = value</td>
- <td class="kt">Assign value to Fault Mask Register (using the instruction
- <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_FAULTMASK (void)</td>
- <td class="kt">M3</td>
- <td class="kt">return FAULTMASK</td>
- <td class="kt">Return Fault Mask Register (using the instruction <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_BASEPRI (uint32_t value)</td>
- <td class="kt">M3</td>
- <td class="kt">BASEPRI = value</td>
- <td class="kt">Set Base Priority (using the instruction <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uiuint32_t __get_BASEPRI (void)</td>
- <td class="kt">M3</td>
- <td class="kt">return BASEPRI</td>
- <td class="kt">Return Base Priority (using the instruction <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_CONTROL (uint32_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">CONTROL = value</td>
- <td class="kt">Set CONTROL register value (using the instruction <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_CONTROL (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return CONTROL</td>
- <td class="kt">Return Control Register Value (using the instruction
- <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_PSP (uint32_t TopOfProcStack)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">PSP = TopOfProcStack</td>
- <td class="kt">Set Process Stack Pointer value (using the instruction
- <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_PSP (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return PSP</td>
- <td class="kt">Return Process Stack Pointer (using the instruction <strong>MRS</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __set_MSP (uint32_t TopOfMainStack)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">MSP = TopOfMainStack</td>
- <td class="kt">Set Main Stack Pointer (using the instruction <strong>MSR</strong>)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __get_MSP (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">return MSP</td>
- <td class="kt">Return Main Stack Pointer (using the instruction <strong>MRS</strong>)</td>
- </tr>
- </tbody>
-</table>
-
-<h3>Cortex-M Instruction Access</h3>
-<p>
- The following functions are defined in <strong>core_cm0.h</strong> / <strong>core_cm3.h</strong>and
- generate specific Cortex-M instructions. The functions are implemented in the file
- <strong>core_cm0.c</strong> / <strong>core_cm3.c</strong>.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt">Name</th>
- <th class="kt">Core</th>
- <th class="kt">Generated CPU Instruction</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __NOP (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">NOP</td>
- <td class="kt">No Operation</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __WFI (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">WFI</td>
- <td class="kt">Wait for Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __WFE (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">WFE</td>
- <td class="kt">Wait for Event</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __SEV (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">SEV</td>
- <td class="kt">Set Event</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __ISB (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">ISB</td>
- <td class="kt">Instruction Synchronization Barrier</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __DSB (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">DSB</td>
- <td class="kt">Data Synchronization Barrier</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __DMB (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">DMB</td>
- <td class="kt">Data Memory Barrier</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __REV (uint32_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">REV</td>
- <td class="kt">Reverse byte order in integer value.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __REV16 (uint16_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">REV16</td>
- <td class="kt">Reverse byte order in unsigned short value. </td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">sint32_t __REVSH (sint16_t value)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">REVSH</td>
- <td class="kt">Reverse byte order in signed short value with sign extension to integer.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __RBIT (uint32_t value)</td>
- <td class="kt">M3</td>
- <td class="kt">RBIT</td>
- <td class="kt">Reverse bit order of value</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint8_t __LDREXB (uint8_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">LDREXB</td>
- <td class="kt">Load exclusive byte</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint16_t __LDREXH (uint16_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">LDREXH</td>
- <td class="kt">Load exclusive half-word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __LDREXW (uint32_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">LDREXW</td>
- <td class="kt">Load exclusive word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint8_t value, uint8_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">STREXB</td>
- <td class="kt">Store exclusive byte</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint16_t value, uint16_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">STREXH</td>
- <td class="kt">Store exclusive half-word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t __STREXB (uint32_t value, uint32_t *addr)</td>
- <td class="kt">M3</td>
- <td class="kt">STREXW</td>
- <td class="kt">Store exclusive word</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void __CLREX (void)</td>
- <td class="kt">M3</td>
- <td class="kt">CLREX</td>
- <td class="kt">Remove the exclusive lock created by __LDREXB, __LDREXH, or __LDREXW</td>
- </tr>
- </tbody>
-</table>
-
-
-<h3>NVIC Access Functions</h3>
-<p>
- The CMSIS provides access to the NVIC via the register interface structure and several helper
- functions that simplify the setup of the NVIC. The CMSIS HAL uses IRQ numbers (IRQn) to
- identify the interrupts. The first device interrupt has the IRQn value 0. Therefore negative
- IRQn values are used for processor core exceptions.
-</p>
-<p>
- For the IRQn values of core exceptions the file <strong><em>device.h</em></strong> provides
- the following enum names.
-</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Core Exception enum Value</th>
- <th class="kt">Core</th>
- <th class="kt">IRQn</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">NonMaskableInt_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-14</td>
- <td class="kt">Cortex-M Non Maskable Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">HardFault_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-13</td>
- <td class="kt">Cortex-M Hard Fault Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">MemoryManagement_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-12</td>
- <td class="kt">Cortex-M Memory Management Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">BusFault_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-11</td>
- <td class="kt">Cortex-M Bus Fault Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">UsageFault_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-10</td>
- <td class="kt">Cortex-M Usage Fault Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">SVCall_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-5</td>
- <td class="kt">Cortex-M SV Call Interrupt </td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">DebugMonitor_IRQn</td>
- <td class="kt">M3</td>
- <td class="kt">-4</td>
- <td class="kt">Cortex-M Debug Monitor Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">PendSV_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-2</td>
- <td class="kt">Cortex-M Pend SV Interrupt</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">SysTick_IRQn</td>
- <td class="kt">M0, M3</td>
- <td class="kt">-1</td>
- <td class="kt">Cortex-M System Tick Interrupt</td>
- </tr>
- </tbody>
-</table>
-
-<p>The following functions simplify the setup of the NVIC.
-The functions are defined as <strong>static inline</strong>.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Core</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SetPriorityGrouping (uint32_t PriorityGroup)</td>
- <td class="kt">M3</td>
- <td class="kt">Priority Grouping Value</td>
- <td class="kt">Set the Priority Grouping (Groups . Subgroups)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriorityGrouping (void)</td>
- <td class="kt">M3</td>
- <td class="kt">(void)</td>
- <td class="kt">Get the Priority Grouping (Groups . Subgroups)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_EnableIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Enable IRQn</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_DisableIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Disable IRQn</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPendingIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Return 1 if IRQn is pending else 0</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SetPendingIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Set IRQn Pending</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_ClearPendingIRQ (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Clear IRQn Pending Status</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetActive (IRQn_Type IRQn)</td>
- <td class="kt">M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Return 1 if IRQn is active else 0</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SetPriority (IRQn_Type IRQn, uint32_t priority)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number, Priority</td>
- <td class="kt">Set Priority for IRQn<br>
- (not threadsafe for Cortex-M0)</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t NVIC_GetPriority (IRQn_Type IRQn)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">IRQ Number</td>
- <td class="kt">Get Priority for IRQn</td>
- </tr>
- <tr>
-<!-- <td class="kt" nowrap="nowrap">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td> -->
- <td class="kt">uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)</td>
- <td class="kt">M3</td>
- <td class="kt">IRQ Number, Priority Group, Preemptive Priority, Sub Priority</td>
- <td class="kt">Encode priority for given group, preemptive and sub priority</td>
- </tr>
-<!-- <td class="kt" nowrap="nowrap">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td> -->
- <td class="kt">NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)</td>
- <td class="kt">M3</td>
- <td class="kt">IRQ Number, Priority, pointer to Priority Group, pointer to Preemptive Priority, pointer to Sub Priority</td>
- <td class="kt">Deccode given priority to group, preemptive and sub priority</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void NVIC_SystemReset (void)</td>
- <td class="kt">M0, M3</td>
- <td class="kt">(void)</td>
- <td class="kt">Resets the System</td>
- </tr>
- </tbody>
-</table>
-<p class="Note">Note</p>
-<ul>
- <li><p>The processor exceptions have negative enum values. Device specific interrupts
- have positive enum values and start with 0. The values are defined in
- <b><em>device.h</em></b> file.
- </p>
- </li>
- <li><p>The values for <b>PreemptPriority</b> and <b>SubPriority</b>
- used in functions <b>NVIC_EncodePriority</b> and <b>NVIC_DecodePriority</b>
- depend on the available __NVIC_PRIO_BITS implemented in the NVIC.
- </p>
- </li>
-</ul>
-
-
-<h3>SysTick Configuration Function</h3>
-
-<p>The following function is used to configure the SysTick timer and start the
-SysTick interrupt.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">uint32_t Sys<span class="style1">TickConfig
- (uint32_t ticks)</span></td>
- <td class="kt">ticks is SysTick counter reload value</td>
- <td class="kt">Setup the SysTick timer and enable the SysTick interrupt. After this
- call the SysTick timer creates interrupts with the specified time
- interval. <br>
- <br>
- Return: 0 when successful, 1 on failure.<br>
- </td>
- </tr>
- </tbody>
-</table>
-
-
-<h3>Cortex-M3 ITM Debug Access</h3>
-
-<p>The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that
-provides together with the Serial Viewer Output trace capabilities for the
-microcontroller system. The ITM has 32 communication channels; two ITM
-communication channels are used by CMSIS to output the following information:</p>
-<ul>
- <li>ITM Channel 0: implements the <strong>ITM_SendChar</strong> function
- which can be used for printf-style output via the debug interface.</li>
- <li>ITM Channel 31: is reserved for the RTOS kernel and can be used for
- kernel awareness debugging.</li>
-</ul>
-<p class="Note">Note</p>
-<ul>
- <li><p>The ITM channel 31 is selected for the RTOS kernel since some kernels
- may use the Privileged level for program execution. ITM
- channels have 4 groups with 8 channels each, whereby each group can be
- configured for access rights in the Unprivileged level. The ITM channel 0
- may be therefore enabled for the user task whereas ITM channel 31 may be
- accessible only in Privileged level from the RTOS kernel itself.</p>
- </li>
-</ul>
-
-<p>The prototype of the <strong>ITM_SendChar</strong> routine is shown in the
-table below.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">void uint32_t ITM_SendChar(uint32_t chr)</td>
- <td class="kt">character to output</td>
- <td class="kt">The function outputs a character via the ITM channel 0. The
- function returns when no debugger is connected that has booked the
- output. It is blocking when a debugger is connected, but the
- previous character send is not transmitted. <br><br>
- Return: the input character 'chr'.</td>
- </tr>
- </tbody>
-</table>
-
-<p>
- Example for the usage of the ITM Channel 31 for RTOS Kernels:
-</p>
-<pre>
- // check if debugger connected and ITM channel enabled for tracing
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
- (ITM->TCR & ITM_TCR_ITMENA) &&
- (ITM->TER & (1UL << 31))) {
- // transmit trace data
- while (ITM->PORT31_U32 == 0);
- ITM->PORT[31].u8 = task_id; // id of next task
- while (ITM->PORT[31].u32 == 0);
- ITM->PORT[31].u32 = task_status; // status information
- }</pre>
-
-
-<h3>Cortex-M3 additional Debug Access</h3>
-
-<p>CMSIS provides additional debug functions to enlarge the Cortex-M3 Debug Access.
-Data can be transmitted via a certain global buffer variable towards the target system.</p>
-
-<p>The buffer variable and the prototypes of the additional functions are shown in the
-table below.</p>
-
-<table class="kt" border="0" cellpadding="0" cellspacing="0">
- <tbody>
- <tr>
- <th class="kt" nowrap="nowrap">Name</th>
- <th class="kt">Parameter</th>
- <th class="kt">Description</th>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">extern volatile int ITM_RxBuffer</td>
- <td class="kt"> </td>
- <td class="kt">Buffer to transmit data towards debug system. <br><br>
- Value 0x5AA55AA5 indicates that buffer is empty.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">int ITM_ReceiveChar (void)</td>
- <td class="kt">none</td>
- <td class="kt">The nonblocking functions returns the character stored in
- ITM_RxBuffer. <br><br>
- Return: -1 indicates that no character was received.</td>
- </tr>
- <tr>
- <td class="kt" nowrap="nowrap">int ITM_CheckChar (void)</td>
- <td class="kt">none</td>
- <td class="kt">The function checks if a character is available in ITM_RxBuffer. <br><br>
- Return: 1 indicates that a character is available, 0 indicates that
- no character is available.</td>
- </tr>
- </tbody>
-</table>
-
-
-<h2><a name="5"></a>CMSIS Example</h2>
-<p>
- The following section shows a typical example for using the CMSIS layer in user applications.
- The example is based on a STM32F10x Device.
-</p>
-<pre>
-#include "stm32f10x.h"
-
-volatile uint32_t msTicks; /* timeTicks counter */
-
-void SysTick_Handler(void) {
- msTicks++; /* increment timeTicks counter */
-}
-
-__INLINE static void Delay (uint32_t dlyTicks) {
- uint32_t curTicks = msTicks;
-
- while ((msTicks - curTicks) < dlyTicks);
-}
-
-__INLINE static void LED_Config(void) {
- ; /* Configure the LEDs */
-}
-
-__INLINE static void LED_On (uint32_t led) {
- ; /* Turn On LED */
-}
-
-__INLINE static void LED_Off (uint32_t led) {
- ; /* Turn Off LED */
-}
-
-int main (void) {
- if (SysTick_Config (SystemCoreClock / 1000)) { /* Setup SysTick for 1 msec interrupts */
- ; /* Handle Error */
- while (1);
- }
-
- LED_Config(); /* configure the LEDs */
-
- while(1) {
- LED_On (0x100); /* Turn on the LED */
- Delay (100); /* delay 100 Msec */
- LED_Off (0x100); /* Turn off the LED */
- Delay (100); /* delay 100 Msec */
- }
-}</pre>
-
-
-</body></html>
\ No newline at end of file diff --git a/contrib/CMSISv1p30_LPC13xx/docs/License.doc b/contrib/CMSISv1p30_LPC13xx/docs/License.doc Binary files differdeleted file mode 100644 index b6b8ace..0000000 --- a/contrib/CMSISv1p30_LPC13xx/docs/License.doc +++ /dev/null diff --git a/contrib/CMSISv1p30_LPC13xx/history.txt b/contrib/CMSISv1p30_LPC13xx/history.txt deleted file mode 100644 index f5a3639..0000000 --- a/contrib/CMSISv1p30_LPC13xx/history.txt +++ /dev/null @@ -1,12 +0,0 @@ -History of updates to CMSISv1p30_LPC13xx
-========================================
-
-18 February 2010
-----------------
-system_LPC13xx.c updated to new version (dated 18 February 2010),
-changing value of SYSPLLCTRL_Val from 0x05 to 0x25
-
-23 March 2010
--------------
-Optimisation level of release build of project changed from
--O2 to -Os.
diff --git a/contrib/CMSISv1p30_LPC13xx/inc/LPC13xx.h b/contrib/CMSISv1p30_LPC13xx/inc/LPC13xx.h deleted file mode 100644 index e428164..0000000 --- a/contrib/CMSISv1p30_LPC13xx/inc/LPC13xx.h +++ /dev/null @@ -1,493 +0,0 @@ -/**************************************************************************//**
- * @file LPC13xx.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
- * NXP LPC13xx Device Series
- * @version V1.01
- * @date 19. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __LPC13xx_H__
-#define __LPC13xx_H__
-
-/*
- * ==========================================================================
- * ---------- Interrupt Number Definition -----------------------------------
- * ==========================================================================
- */
-
-typedef enum IRQn
-{
-/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
- BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
- SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
-
-/****** LPC13xx Specific Interrupt Numbers *******************************************************/
- WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
- WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */
- WAKEUP2_IRQn = 2,
- WAKEUP3_IRQn = 3,
- WAKEUP4_IRQn = 4,
- WAKEUP5_IRQn = 5,
- WAKEUP6_IRQn = 6,
- WAKEUP7_IRQn = 7,
- WAKEUP8_IRQn = 8,
- WAKEUP9_IRQn = 9,
- WAKEUP10_IRQn = 10,
- WAKEUP11_IRQn = 11,
- WAKEUP12_IRQn = 12,
- WAKEUP13_IRQn = 13,
- WAKEUP14_IRQn = 14,
- WAKEUP15_IRQn = 15,
- WAKEUP16_IRQn = 16,
- WAKEUP17_IRQn = 17,
- WAKEUP18_IRQn = 18,
- WAKEUP19_IRQn = 19,
- WAKEUP20_IRQn = 20,
- WAKEUP21_IRQn = 21,
- WAKEUP22_IRQn = 22,
- WAKEUP23_IRQn = 23,
- WAKEUP24_IRQn = 24,
- WAKEUP25_IRQn = 25,
- WAKEUP26_IRQn = 26,
- WAKEUP27_IRQn = 27,
- WAKEUP28_IRQn = 28,
- WAKEUP29_IRQn = 29,
- WAKEUP30_IRQn = 30,
- WAKEUP31_IRQn = 31,
- WAKEUP32_IRQn = 32,
- WAKEUP33_IRQn = 33,
- WAKEUP34_IRQn = 34,
- WAKEUP35_IRQn = 35,
- WAKEUP36_IRQn = 36,
- WAKEUP37_IRQn = 37,
- WAKEUP38_IRQn = 38,
- WAKEUP39_IRQn = 39,
- I2C_IRQn = 40, /*!< I2C Interrupt */
- TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */
- TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */
- TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */
- TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */
- SSP_IRQn = 45, /*!< SSP Interrupt */
- UART_IRQn = 46, /*!< UART Interrupt */
- USB_IRQn = 47, /*!< USB Regular Interrupt */
- USB_FIQn = 48, /*!< USB Fast Interrupt */
- ADC_IRQn = 49, /*!< A/D Converter Interrupt */
- WDT_IRQn = 50, /*!< Watchdog timer Interrupt */
- BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */
- EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */
- EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */
- EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */
- EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */
-} IRQn_Type;
-
-
-/*
- * ==========================================================================
- * ----------- Processor and Core Peripheral Section ------------------------
- * ==========================================================================
- */
-
-/* Configuration of the Cortex-M3 Processor and Core Peripherals */
-#define __MPU_PRESENT 1 /*!< MPU present or not */
-#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-
-#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
-#include "system_LPC13xx.h" /* System Header */
-
-
-/******************************************************************************/
-/* Device Specific Peripheral registers structures */
-/******************************************************************************/
-
-#if defined ( __CC_ARM )
-#pragma anon_unions
-#endif
-
-/*------------- System Control (SYSCON) --------------------------------------*/
-typedef struct
-{
- __IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */
- __IO uint32_t PRESETCTRL;
- __IO uint32_t SYSPLLCTRL; /* Sys PLL control */
- __IO uint32_t SYSPLLSTAT;
- __IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */
- __IO uint32_t USBPLLSTAT;
- uint32_t RESERVED0[2];
-
- __IO uint32_t SYSOSCCTRL; /* Offset 0x20 */
- __IO uint32_t WDTOSCCTRL;
- __IO uint32_t IRCCTRL;
- uint32_t RESERVED1[1];
- __IO uint32_t SYSRESSTAT; /* Offset 0x30 */
- uint32_t RESERVED2[3];
- __IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */
- __IO uint32_t SYSPLLCLKUEN;
- __IO uint32_t USBPLLCLKSEL;
- __IO uint32_t USBPLLCLKUEN;
- uint32_t RESERVED3[8];
-
- __IO uint32_t MAINCLKSEL; /* Offset 0x70 */
- __IO uint32_t MAINCLKUEN;
- __IO uint32_t SYSAHBCLKDIV;
- uint32_t RESERVED4[1];
-
- __IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */
- uint32_t RESERVED5[4];
- __IO uint32_t SSPCLKDIV;
- __IO uint32_t UARTCLKDIV;
- uint32_t RESERVED6[4];
- __IO uint32_t TRACECLKDIV;
-
- __IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */
- uint32_t RESERVED7[3];
-
- __IO uint32_t USBCLKSEL; /* Offset 0xC0 */
- __IO uint32_t USBCLKUEN;
- __IO uint32_t USBCLKDIV;
- uint32_t RESERVED8[1];
- __IO uint32_t WDTCLKSEL; /* Offset 0xD0 */
- __IO uint32_t WDTCLKUEN;
- __IO uint32_t WDTCLKDIV;
- uint32_t RESERVED9[1];
- __IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */
- __IO uint32_t CLKOUTUEN;
- __IO uint32_t CLKOUTDIV;
- uint32_t RESERVED10[5];
-
- __IO uint32_t PIOPORCAP0; /* Offset 0x100 */
- __IO uint32_t PIOPORCAP1;
- uint32_t RESERVED11[18];
-
- __IO uint32_t BODCTRL; /* Offset 0x150 */
- uint32_t RESERVED12[1];
- __IO uint32_t SYSTCKCAL;
- uint32_t RESERVED13[41];
-
- __IO uint32_t STARTAPRP0; /* Offset 0x200 */
- __IO uint32_t STARTERP0;
- __IO uint32_t STARTRSRP0CLR;
- __IO uint32_t STARTSRP0;
- __IO uint32_t STARTAPRP1;
- __IO uint32_t STARTERP1;
- __IO uint32_t STARTRSRP1CLR;
- __IO uint32_t STARTSRP1;
- uint32_t RESERVED14[4];
-
- __IO uint32_t PDSLEEPCFG; /* Offset 0x230 */
- __IO uint32_t PDAWAKECFG;
- __IO uint32_t PDRUNCFG;
- uint32_t RESERVED15[110];
- __I uint32_t DEVICE_ID;
-} LPC_SYSCON_TypeDef;
-
-
-/*------------- Pin Connect Block (IOCON) --------------------------------*/
-typedef struct
-{
- __IO uint32_t PIO2_6;
- uint32_t RESERVED0[1];
- __IO uint32_t PIO2_0;
- __IO uint32_t RESET_PIO0_0;
- __IO uint32_t PIO0_1;
- __IO uint32_t PIO1_8;
- uint32_t RESERVED1[1];
- __IO uint32_t PIO0_2;
-
- __IO uint32_t PIO2_7;
- __IO uint32_t PIO2_8;
- __IO uint32_t PIO2_1;
- __IO uint32_t PIO0_3;
- __IO uint32_t PIO0_4;
- __IO uint32_t PIO0_5;
- __IO uint32_t PIO1_9;
- __IO uint32_t PIO3_4;
-
- __IO uint32_t PIO2_4;
- __IO uint32_t PIO2_5;
- __IO uint32_t PIO3_5;
- __IO uint32_t PIO0_6;
- __IO uint32_t PIO0_7;
- __IO uint32_t PIO2_9;
- __IO uint32_t PIO2_10;
- __IO uint32_t PIO2_2;
-
- __IO uint32_t PIO0_8;
- __IO uint32_t PIO0_9;
- __IO uint32_t JTAG_TCK_PIO0_10;
- __IO uint32_t PIO1_10;
- __IO uint32_t PIO2_11;
- __IO uint32_t JTAG_TDI_PIO0_11;
- __IO uint32_t JTAG_TMS_PIO1_0;
- __IO uint32_t JTAG_TDO_PIO1_1;
-
- __IO uint32_t JTAG_nTRST_PIO1_2;
- __IO uint32_t PIO3_0;
- __IO uint32_t PIO3_1;
- __IO uint32_t PIO2_3;
- __IO uint32_t ARM_SWDIO_PIO1_3;
- __IO uint32_t PIO1_4;
- __IO uint32_t PIO1_11;
- __IO uint32_t PIO3_2;
-
- __IO uint32_t PIO1_5;
- __IO uint32_t PIO1_6;
- __IO uint32_t PIO1_7;
- __IO uint32_t PIO3_3;
- __IO uint32_t SCKLOC; /* For HB1 only, new feature */
-} LPC_IOCON_TypeDef;
-
-
-/*------------- Power Management Unit (PMU) --------------------------*/
-typedef struct
-{
- __IO uint32_t PCON;
- __IO uint32_t GPREG0;
- __IO uint32_t GPREG1;
- __IO uint32_t GPREG2;
- __IO uint32_t GPREG3;
- __IO uint32_t GPREG4;
-} LPC_PMU_TypeDef;
-
-
-/*------------- General Purpose Input/Output (GPIO) --------------------------*/
-typedef struct
-{
- union {
- __IO uint32_t MASKED_ACCESS[4096];
- struct {
- uint32_t RESERVED0[4095];
- __IO uint32_t DATA;
- };
- };
- uint32_t RESERVED1[4096];
- __IO uint32_t DIR;
- __IO uint32_t IS;
- __IO uint32_t IBE;
- __IO uint32_t IEV;
- __IO uint32_t IE;
- __IO uint32_t RIS;
- __IO uint32_t MIS;
- __IO uint32_t IC;
-} LPC_GPIO_TypeDef;
-
-
-/*------------- Timer (TMR) --------------------------------------------------*/
-typedef struct
-{
- __IO uint32_t IR;
- __IO uint32_t TCR;
- __IO uint32_t TC;
- __IO uint32_t PR;
- __IO uint32_t PC;
- __IO uint32_t MCR;
- __IO uint32_t MR0;
- __IO uint32_t MR1;
- __IO uint32_t MR2;
- __IO uint32_t MR3;
- __IO uint32_t CCR;
- __I uint32_t CR0;
- uint32_t RESERVED1[3];
- __IO uint32_t EMR;
- uint32_t RESERVED2[12];
- __IO uint32_t CTCR;
- __IO uint32_t PWMC;
-} LPC_TMR_TypeDef;
-
-/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
-typedef struct
-{
- union {
- __I uint32_t RBR;
- __O uint32_t THR;
- __IO uint32_t DLL;
- };
- union {
- __IO uint32_t DLM;
- __IO uint32_t IER;
- };
- union {
- __I uint32_t IIR;
- __O uint32_t FCR;
- };
- __IO uint32_t LCR;
- __IO uint32_t MCR;
- __I uint32_t LSR;
- __I uint32_t MSR;
- __IO uint32_t SCR;
- __IO uint32_t ACR;
- __IO uint32_t ICR;
- __IO uint32_t FDR;
- uint32_t RESERVED0;
- __IO uint32_t TER;
- uint32_t RESERVED1[6];
- __IO uint32_t RS485CTRL;
- __IO uint32_t ADRMATCH;
- __IO uint32_t RS485DLY;
- __I uint32_t FIFOLVL;
-} LPC_UART_TypeDef;
-
-/*------------- Synchronous Serial Communication (SSP) -----------------------*/
-typedef struct
-{
- __IO uint32_t CR0;
- __IO uint32_t CR1;
- __IO uint32_t DR;
- __I uint32_t SR;
- __IO uint32_t CPSR;
- __IO uint32_t IMSC;
- __IO uint32_t RIS;
- __IO uint32_t MIS;
- __IO uint32_t ICR;
-} LPC_SSP_TypeDef;
-
-/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
-typedef struct
-{
- __IO uint32_t CONSET;
- __I uint32_t STAT;
- __IO uint32_t DAT;
- __IO uint32_t ADR0;
- __IO uint32_t SCLH;
- __IO uint32_t SCLL;
- __O uint32_t CONCLR;
- __IO uint32_t MMCTRL;
- __IO uint32_t ADR1;
- __IO uint32_t ADR2;
- __IO uint32_t ADR3;
- __I uint32_t DATA_BUFFER;
- __IO uint32_t MASK0;
- __IO uint32_t MASK1;
- __IO uint32_t MASK2;
- __IO uint32_t MASK3;
-} LPC_I2C_TypeDef;
-
-/*------------- Watchdog Timer (WDT) -----------------------------------------*/
-typedef struct
-{
- __IO uint32_t MOD;
- __IO uint32_t TC;
- __O uint32_t FEED;
- __I uint32_t TV;
-} LPC_WDT_TypeDef;
-
-/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
-typedef struct
-{
- __IO uint32_t CR;
- __IO uint32_t GDR;
- uint32_t RESERVED0;
- __IO uint32_t INTEN;
- __I uint32_t DR0;
- __I uint32_t DR1;
- __I uint32_t DR2;
- __I uint32_t DR3;
- __I uint32_t DR4;
- __I uint32_t DR5;
- __I uint32_t DR6;
- __I uint32_t DR7;
- __I uint32_t STAT;
-} LPC_ADC_TypeDef;
-
-
-/*------------- Universal Serial Bus (USB) -----------------------------------*/
-typedef struct
-{
- __I uint32_t DevIntSt; /* USB Device Interrupt Registers */
- __IO uint32_t DevIntEn;
- __O uint32_t DevIntClr;
- __O uint32_t DevIntSet;
-
- __O uint32_t CmdCode; /* USB Device SIE Command Registers */
- __I uint32_t CmdData;
-
- __I uint32_t RxData; /* USB Device Transfer Registers */
- __O uint32_t TxData;
- __I uint32_t RxPLen;
- __O uint32_t TxPLen;
- __IO uint32_t Ctrl;
- __O uint32_t DevFIQSel;
-} LPC_USB_TypeDef;
-
-#if defined ( __CC_ARM )
-#pragma no_anon_unions
-#endif
-
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-/* Base addresses */
-#define LPC_FLASH_BASE (0x00000000UL)
-#define LPC_RAM_BASE (0x10000000UL)
-#define LPC_APB0_BASE (0x40000000UL)
-#define LPC_AHB_BASE (0x50000000UL)
-
-/* APB0 peripherals */
-#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
-#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
-#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
-#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
-#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
-#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
-#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
-#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
-#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000)
-#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
-#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000)
-#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
-#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
-
-/* AHB peripherals */
-#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
-#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
-#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
-#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
-#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
-
-/******************************************************************************/
-/* Peripheral declaration */
-/******************************************************************************/
-#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
-#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
-#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
-#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
-#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
-#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
-#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
-#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
-#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
-#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE )
-#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
-#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
-#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
-#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
-#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
-#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
-#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
-
-#endif // __LPC13xx_H__
diff --git a/contrib/CMSISv1p30_LPC13xx/inc/core_cm3.h b/contrib/CMSISv1p30_LPC13xx/inc/core_cm3.h deleted file mode 100644 index 2b6b51a..0000000 --- a/contrib/CMSISv1p30_LPC13xx/inc/core_cm3.h +++ /dev/null @@ -1,1818 +0,0 @@ -/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#ifndef __CM3_CORE_H__
-#define __CM3_CORE_H__
-
-/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
- *
- * List of Lint messages which will be suppressed and not shown:
- * - Error 10: \n
- * register uint32_t __regBasePri __asm("basepri"); \n
- * Error 10: Expecting ';'
- * .
- * - Error 530: \n
- * return(__regBasePri); \n
- * Warning 530: Symbol '__regBasePri' (line 264) not initialized
- * .
- * - Error 550: \n
- * __regBasePri = (basePri & 0x1ff); \n
- * Warning 550: Symbol '__regBasePri' (line 271) not accessed
- * .
- * - Error 754: \n
- * uint32_t RESERVED0[24]; \n
- * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
- * .
- * - Error 750: \n
- * #define __CM3_CORE_H__ \n
- * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
- * .
- * - Error 528: \n
- * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
- * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
- * .
- * - Error 751: \n
- * } InterruptType_Type; \n
- * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
- * .
- * Note: To re-enable a Message, insert a space before 'lint' *
- *
- */
-
-/*lint -save */
-/*lint -e10 */
-/*lint -e530 */
-/*lint -e550 */
-/*lint -e754 */
-/*lint -e750 */
-/*lint -e528 */
-/*lint -e751 */
-
-
-/** @addtogroup CMSIS_CM3_core_definitions CM3 Core Definitions
- This file defines all structures and symbols for CMSIS core:
- - CMSIS version number
- - Cortex-M core registers and bitfields
- - Cortex-M core peripheral base address
- @{
- */
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex core */
-
-#include <stdint.h> /* Include standard types */
-
-#if defined (__ICCARM__)
- #include <intrinsics.h> /* IAR Intrinsics */
-#endif
-
-
-#ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
-#endif
-
-
-
-
-/**
- * IO definitions
- *
- * define access restrictions to peripheral registers
- */
-
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- ******************************************************************************/
-/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
- @{
-*/
-
-
-/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
- memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
- @{
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 Software Trigger Interrupt Register */
-} NVIC_Type;
-/*@}*/ /* end of group CMSIS_CM3_NVIC */
-
-
-/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
- memory mapped structure for System Control Block (SCB)
- @{
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x00 CPU ID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x04 Interrupt Control State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x08 Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x0C Application Interrupt / Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x10 System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x14 Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x24 System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x28 Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x2C Hard Fault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x30 Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x34 Mem Manage Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x38 Bus Fault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x3C Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x40 Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x48 Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x4C Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x50 Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x60 ISA Feature Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-/*@}*/ /* end of group CMSIS_CM3_SCB */
-
-
-/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
- memory mapped structure for SysTick
- @{
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-/*@}*/ /* end of group CMSIS_CM3_SysTick */
-
-
-/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
- memory mapped structure for Instrumentation Trace Macrocell (ITM)
- @{
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x00 ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __IO uint32_t IWR; /*!< Offset: ITM Integration Write Register */
- __IO uint32_t IRR; /*!< Offset: ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __IO uint32_t LAR; /*!< Offset: ITM Lock Access Register */
- __IO uint32_t LSR; /*!< Offset: ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-/*@}*/ /* end of group CMSIS_CM3_ITM */
-
-
-/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
- memory mapped structure for Interrupt Type
- @{
- */
-typedef struct
-{
- uint32_t RESERVED0;
- __I uint32_t ICTR; /*!< Offset: 0x04 Interrupt Control Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x08 Auxiliary Control Register */
-#else
- uint32_t RESERVED1;
-#endif
-} InterruptType_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define InterruptType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
-#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define InterruptType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
-#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
-
-#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
-#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
-
-#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
-#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
-/*@}*/ /* end of group CMSIS_CM3_InterruptType */
-
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
-/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
- memory mapped structure for Memory Protection Unit (MPU)
- @{
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x00 MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x04 MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x08 MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x0C MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x10 MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x14 MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x1C MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x24 MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
-#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
-#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
-#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
-#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
-#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
-#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@}*/ /* end of group CMSIS_CM3_MPU */
-#endif
-
-
-/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
- memory mapped structure for Core Debug Register
- @{
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x00 Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x04 Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x08 Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x0C Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-/*@}*/ /* end of group CMSIS_CM3_CoreDebug */
-
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
-#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
-
-#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
-#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_register */
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#define __enable_fault_irq __enable_fiq
-#define __disable_fault_irq __disable_fiq
-
-#define __NOP __nop
-#define __WFI __wfi
-#define __WFE __wfe
-#define __SEV __sev
-#define __ISB() __isb(0)
-#define __DSB() __dsb(0)
-#define __DMB() __dmb(0)
-#define __REV __rev
-#define __RBIT __rbit
-#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
-#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
-#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
-#define __STREXB(value, ptr) __strex(value, ptr)
-#define __STREXH(value, ptr) __strex(value, ptr)
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
-/* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-extern void __CLREX(void);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-#else /* (__ARMCC_VERSION >= 400000) */
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-#define __CLREX __clrex
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-static __INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-static __INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-static __INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-static __INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-static __INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-static __INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & 1);
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-static __INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-static __INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
-#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
-
-static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
-
-#define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
-static __INLINE void __WFI() { __ASM ("wfi"); }
-static __INLINE void __WFE() { __ASM ("wfe"); }
-static __INLINE void __SEV() { __ASM ("sev"); }
-static __INLINE void __CLREX() { __ASM ("clrex"); }
-
-/* intrinsic void __ISB(void) */
-/* intrinsic void __DSB(void) */
-/* intrinsic void __DMB(void) */
-/* intrinsic void __set_PRIMASK(); */
-/* intrinsic void __get_PRIMASK(); */
-/* intrinsic void __set_FAULTMASK(); */
-/* intrinsic void __get_FAULTMASK(); */
-/* intrinsic uint32_t __REV(uint32_t value); */
-/* intrinsic uint32_t __REVSH(uint32_t value); */
-/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
-/* intrinsic unsigned long __LDREX(unsigned long *); */
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
-static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
-
-static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
-static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
-
-static __INLINE void __NOP() { __ASM volatile ("nop"); }
-static __INLINE void __WFI() { __ASM volatile ("wfi"); }
-static __INLINE void __WFE() { __ASM volatile ("wfe"); }
-static __INLINE void __SEV() { __ASM volatile ("sev"); }
-static __INLINE void __ISB() { __ASM volatile ("isb"); }
-static __INLINE void __DSB() { __ASM volatile ("dsb"); }
-static __INLINE void __DMB() { __ASM volatile ("dmb"); }
-static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
-
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-extern uint32_t __get_PSP(void);
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-extern void __set_PSP(uint32_t topOfProcStack);
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-extern uint32_t __get_MSP(void);
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-extern void __set_MSP(uint32_t topOfMainStack);
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-extern uint32_t __get_BASEPRI(void);
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-extern void __set_BASEPRI(uint32_t basePri);
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-extern uint32_t __get_PRIMASK(void);
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-extern void __set_PRIMASK(uint32_t priMask);
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-extern uint32_t __get_FAULTMASK(void);
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-extern void __set_FAULTMASK(uint32_t faultMask);
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-extern uint32_t __get_CONTROL(void);
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-extern void __set_CONTROL(uint32_t control);
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-extern uint32_t __REV(uint32_t value);
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-extern uint32_t __REV16(uint16_t value);
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-extern int32_t __REVSH(int16_t value);
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-extern uint32_t __RBIT(uint32_t value);
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-extern uint8_t __LDREXB(uint8_t *addr);
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-extern uint16_t __LDREXH(uint16_t *addr);
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-extern uint32_t __LDREXW(uint32_t *addr);
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-
-/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
- Core Function Interface containing:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Reset Functions
-*/
-/*@{*/
-
-/* ########################## NVIC functions #################################### */
-
-/**
- * @brief Set the Priority Grouping in NVIC Interrupt Controller
- *
- * @param PriorityGroup is priority grouping field
- *
- * Set the priority grouping field using the required unlock sequence.
- * The parameter priority_grouping is assigned to the field
- * SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- */
-static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- (0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-/**
- * @brief Get the Priority Grouping from NVIC Interrupt Controller
- *
- * @return priority grouping field
- *
- * Get the priority grouping from NVIC Interrupt Controller.
- * priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
- */
-static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-/**
- * @brief Enable Interrupt in NVIC Interrupt Controller
- *
- * @param IRQn The positive number of the external interrupt to enable
- *
- * Enable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-/**
- * @brief Disable the interrupt line for external interrupt specified
- *
- * @param IRQn The positive number of the external interrupt to disable
- *
- * Disable a device specific interupt in the NVIC interrupt controller.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-/**
- * @brief Read the interrupt pending bit for a device specific interrupt source
- *
- * @param IRQn The number of the device specifc interrupt
- * @return 1 = interrupt pending, 0 = interrupt not pending
- *
- * Read the pending register in NVIC and return 1 if its status is pending,
- * otherwise it returns 0
- */
-static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-/**
- * @brief Set the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for set pending
- *
- * Set the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-/**
- * @brief Clear the pending bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for clear pending
- *
- * Clear the pending bit for the specified interrupt.
- * The interrupt number cannot be a negative value.
- */
-static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-/**
- * @brief Read the active bit for an external interrupt
- *
- * @param IRQn The number of the interrupt for read active bit
- * @return 1 = interrupt active, 0 = interrupt not active
- *
- * Read the active register in NVIC and returns 1 if its status is active,
- * otherwise it returns 0.
- */
-static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-/**
- * @brief Set the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for set priority
- * @param priority The priority to set
- *
- * Set the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-/**
- * @brief Read the priority for an interrupt
- *
- * @param IRQn The number of the interrupt for get priority
- * @return The priority for the interrupt
- *
- * Read the priority for the specified interrupt. The interrupt
- * number can be positive to specify an external (device specific)
- * interrupt, or negative to specify an internal (core) interrupt.
- *
- * The returned priority value is automatically aligned to the implemented
- * priority bits of the microcontroller.
- *
- * Note: The priority cannot be set for every core interrupt.
- */
-static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/**
- * @brief Encode the priority for an interrupt
- *
- * @param PriorityGroup The used priority group
- * @param PreemptPriority The preemptive priority value (starting from 0)
- * @param SubPriority The sub priority value (starting from 0)
- * @return The encoded priority for the interrupt
- *
- * Encode the priority for an interrupt with the given priority group,
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The returned priority value can be used for NVIC_SetPriority(...) function
- */
-static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/**
- * @brief Decode the priority of an interrupt
- *
- * @param Priority The priority for the interrupt
- * @param PriorityGroup The used priority group
- * @param pPreemptPriority The preemptive priority value (starting from 0)
- * @param pSubPriority The sub priority value (starting from 0)
- *
- * Decode an interrupt priority value with the given priority group to
- * preemptive priority value and sub priority value.
- * In case of a conflict between priority grouping and available
- * priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
- *
- * The priority value can be retrieved with NVIC_GetPriority(...) function
- */
-static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-
-/* ################################## SysTick function ############################################ */
-
-#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
-
-/**
- * @brief Initialize and start the SysTick counter and its interrupt.
- *
- * @param ticks number of ticks between two interrupts
- * @return 1 = failed, 0 = successful
- *
- * Initialise the system tick timer and its interrupt and start the
- * system tick timer / counter in free running mode to generate
- * periodical interrupts.
- */
-static __INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-
-
-
-/* ################################## Reset function ############################################ */
-
-/**
- * @brief Initiate a system reset request.
- *
- * Initiate a system reset request to reset the MCU
- */
-static __INLINE void NVIC_SystemReset(void)
-{
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@}*/ /* end of group CMSIS_CM3_Core_FunctionInterface */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-
-/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
- Core Debug Interface containing:
- - Core Debug Receive / Transmit Functions
- - Core Debug Defines
- - Core Debug Variables
-*/
-/*@{*/
-
-extern volatile int ITM_RxBuffer; /*!< variable to receive characters */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
-
-
-/**
- * @brief Outputs a character via the ITM channel 0
- *
- * @param ch character to output
- * @return character to output
- *
- * The function outputs a character via the ITM channel 0.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
- */
-static __INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
- (ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/**
- * @brief Inputs a character via variable ITM_RxBuffer
- *
- * @return received character, -1 = no character received
- *
- * The function inputs a character via variable ITM_RxBuffer.
- * The function returns when no debugger is connected that has booked the output.
- * It is blocking when a debugger is connected, but the previous character send is not transmitted.
- */
-static __INLINE int ITM_ReceiveChar (void) {
- int ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- * @brief Check if a character via variable ITM_RxBuffer is available
- *
- * @return 1 = character available, 0 = no character available
- *
- * The function checks variable ITM_RxBuffer whether a character is available or not.
- * The function returns '1' if a character is available and '0' if no character is available.
- */
-static __INLINE int ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@}*/ /* end of group CMSIS_CM3_core_DebugInterface */
-
-
-#ifdef __cplusplus
-}
-#endif
-
-/*@}*/ /* end of group CMSIS_CM3_core_definitions */
-
-#endif /* __CM3_CORE_H__ */
-
-/*lint -restore */
diff --git a/contrib/CMSISv1p30_LPC13xx/inc/system_LPC13xx.h b/contrib/CMSISv1p30_LPC13xx/inc/system_LPC13xx.h deleted file mode 100644 index 5b9f2ff..0000000 --- a/contrib/CMSISv1p30_LPC13xx/inc/system_LPC13xx.h +++ /dev/null @@ -1,64 +0,0 @@ -/**************************************************************************//**
- * @file system_LPC13xx.h
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
- * for the NXP LPC13xx Device Series
- * @version V1.01
- * @date 19. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-
-#ifndef __SYSTEM_LPC13xx_H
-#define __SYSTEM_LPC13xx_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System and update the SystemCoreClock variable.
- */
-extern void SystemInit (void);
-
-/**
- * Update SystemCoreClock variable
- *
- * @param none
- * @return none
- *
- * @brief Updates the SystemCoreClock with current core Clock
- * retrieved from cpu registers.
- */
-extern void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __SYSTEM_LPC13x_H */
diff --git a/contrib/CMSISv1p30_LPC13xx/src/core_cm3.c b/contrib/CMSISv1p30_LPC13xx/src/core_cm3.c deleted file mode 100644 index 56fddc5..0000000 --- a/contrib/CMSISv1p30_LPC13xx/src/core_cm3.c +++ /dev/null @@ -1,784 +0,0 @@ -/**************************************************************************//**
- * @file core_cm3.c
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
- * @version V1.30
- * @date 30. October 2009
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-__ASM uint32_t __get_PSP(void)
-{
- mrs r0, psp
- bx lr
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-__ASM void __set_PSP(uint32_t topOfProcStack)
-{
- msr psp, r0
- bx lr
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-__ASM uint32_t __get_MSP(void)
-{
- mrs r0, msp
- bx lr
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-__ASM void __set_MSP(uint32_t mainStackPointer)
-{
- msr msp, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-__ASM uint32_t __REV16(uint16_t value)
-{
- rev16 r0, r0
- bx lr
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-__ASM int32_t __REVSH(int16_t value)
-{
- revsh r0, r0
- bx lr
-}
-
-
-#if (__ARMCC_VERSION < 400000)
-
-/**
- * @brief Remove the exclusive lock created by ldrex
- *
- * Removes the exclusive lock which is created by ldrex.
- */
-__ASM void __CLREX(void)
-{
- clrex
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-__ASM uint32_t __get_BASEPRI(void)
-{
- mrs r0, basepri
- bx lr
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-__ASM void __set_BASEPRI(uint32_t basePri)
-{
- msr basepri, r0
- bx lr
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-__ASM uint32_t __get_PRIMASK(void)
-{
- mrs r0, primask
- bx lr
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-__ASM void __set_PRIMASK(uint32_t priMask)
-{
- msr primask, r0
- bx lr
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-__ASM uint32_t __get_FAULTMASK(void)
-{
- mrs r0, faultmask
- bx lr
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-__ASM void __set_FAULTMASK(uint32_t faultMask)
-{
- msr faultmask, r0
- bx lr
-}
-
-/**
- * @brief Return the Control Register value
- *
- * @return Control value
- *
- * Return the content of the control register
- */
-__ASM uint32_t __get_CONTROL(void)
-{
- mrs r0, control
- bx lr
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-__ASM void __set_CONTROL(uint32_t control)
-{
- msr control, r0
- bx lr
-}
-
-#endif /* __ARMCC_VERSION */
-
-
-
-#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-#pragma diag_suppress=Pe940
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void)
-{
- __ASM("mrs r0, psp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM("msr psp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void)
-{
- __ASM("mrs r0, msp");
- __ASM("bx lr");
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM("msr msp, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- __ASM("rev16 r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- __ASM("rbit r0, r0");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit values)
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- __ASM("ldrexb r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- __ASM("ldrexh r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- __ASM("ldrex r0, [r0]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- __ASM("strexb r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- __ASM("strexh r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- __ASM("strex r0, r0, [r1]");
- __ASM("bx lr");
-}
-
-#pragma diag_default=Pe940
-
-
-#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/**
- * @brief Return the Process Stack Pointer
- *
- * @return ProcessStackPointer
- *
- * Return the actual process stack pointer
- */
-uint32_t __get_PSP(void) __attribute__( ( naked ) );
-uint32_t __get_PSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, psp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Process Stack Pointer
- *
- * @param topOfProcStack Process Stack Pointer
- *
- * Assign the value ProcessStackPointer to the MSP
- * (process stack pointer) Cortex processor register
- */
-void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
-void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfProcStack) );
-}
-
-/**
- * @brief Return the Main Stack Pointer
- *
- * @return Main Stack Pointer
- *
- * Return the current value of the MSP (main stack pointer)
- * Cortex processor register
- */
-uint32_t __get_MSP(void) __attribute__( ( naked ) );
-uint32_t __get_MSP(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, msp\n\t"
- "MOV r0, %0 \n\t"
- "BX lr \n\t" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Main Stack Pointer
- *
- * @param topOfMainStack Main Stack Pointer
- *
- * Assign the value mainStackPointer to the MSP
- * (main stack pointer) Cortex processor register
- */
-void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
-void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n\t"
- "BX lr \n\t" : : "r" (topOfMainStack) );
-}
-
-/**
- * @brief Return the Base Priority value
- *
- * @return BasePriority
- *
- * Return the content of the base priority register
- */
-uint32_t __get_BASEPRI(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Base Priority value
- *
- * @param basePri BasePriority
- *
- * Set the base priority register
- */
-void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) );
-}
-
-/**
- * @brief Return the Priority Mask value
- *
- * @return PriMask
- *
- * Return state of the priority mask bit from the priority mask register
- */
-uint32_t __get_PRIMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Priority Mask value
- *
- * @param priMask PriMask
- *
- * Set the priority mask bit in the priority mask register
- */
-void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
-}
-
-/**
- * @brief Return the Fault Mask value
- *
- * @return FaultMask
- *
- * Return the content of the fault mask register
- */
-uint32_t __get_FAULTMASK(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Fault Mask value
- *
- * @param faultMask faultMask value
- *
- * Set the fault mask register
- */
-void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
-}
-
-/**
- * @brief Return the Control Register value
-*
-* @return Control value
- *
- * Return the content of the control register
- */
-uint32_t __get_CONTROL(void)
-{
- uint32_t result=0;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-/**
- * @brief Set the Control Register value
- *
- * @param control Control value
- *
- * Set the control register
- */
-void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) );
-}
-
-
-/**
- * @brief Reverse byte order in integer value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in integer value
- */
-uint32_t __REV(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in unsigned short value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in unsigned short value
- */
-uint32_t __REV16(uint16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse byte order in signed short value with sign extension to integer
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse byte order in signed short value with sign extension to integer
- */
-int32_t __REVSH(int16_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief Reverse bit order of value
- *
- * @param value value to reverse
- * @return reversed value
- *
- * Reverse bit order of value
- */
-uint32_t __RBIT(uint32_t value)
-{
- uint32_t result=0;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (8 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 8 bit value
- */
-uint8_t __LDREXB(uint8_t *addr)
-{
- uint8_t result=0;
-
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (16 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 16 bit values
- */
-uint16_t __LDREXH(uint16_t *addr)
-{
- uint16_t result=0;
-
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief LDR Exclusive (32 bit)
- *
- * @param *addr address pointer
- * @return value of (*address)
- *
- * Exclusive LDR command for 32 bit values
- */
-uint32_t __LDREXW(uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (8 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 8 bit values
- */
-uint32_t __STREXB(uint8_t value, uint8_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (16 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 16 bit values
- */
-uint32_t __STREXH(uint16_t value, uint16_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-/**
- * @brief STR Exclusive (32 bit)
- *
- * @param value value to store
- * @param *addr address pointer
- * @return successful / failed
- *
- * Exclusive STR command for 32 bit values
- */
-uint32_t __STREXW(uint32_t value, uint32_t *addr)
-{
- uint32_t result=0;
-
- __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
- return(result);
-}
-
-
-#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
diff --git a/contrib/CMSISv1p30_LPC13xx/src/system_LPC13xx.c b/contrib/CMSISv1p30_LPC13xx/src/system_LPC13xx.c deleted file mode 100644 index 3caaf6b..0000000 --- a/contrib/CMSISv1p30_LPC13xx/src/system_LPC13xx.c +++ /dev/null @@ -1,487 +0,0 @@ -/**************************************************************************//**
- * @file system_LPC13xx.c
- * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
- * for the NXP LPC13xx Device Series
- * @version V1.02
- * @date 18. February 2010
- *
- * @note
- * Copyright (C) 2009 ARM Limited. All rights reserved.
- *
- * @par
- * ARM Limited (ARM) is supplying this software for use with Cortex-M
- * processor based microcontrollers. This file can be freely distributed
- * within development tools that are supporting such ARM based processors.
- *
- * @par
- * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
- * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
- * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
- * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
- *
- ******************************************************************************/
-
-// ******** Code Red **************
-// * Changed USBCLK_SETUP to 1
-// * Changed SYSPLLCTRL_Val to 0x25
-// ********************************
-
-#include <stdint.h>
-#include "LPC13xx.h"
-
-/*
-//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
-*/
-
-/*--------------------- Clock Configuration ----------------------------------
-//
-// <e> Clock Configuration
-// <e1> System Clock Setup
-// <e2> System Oscillator Enable
-// <o3.1> Select System Oscillator Frequency Range
-// <0=> 1 - 20 MHz
-// <1=> 15 - 25 MHz
-// </e2>
-// <e4> Watchdog Oscillator Enable
-// <o5.0..4> Select Divider for Fclkana
-// <0=> 2 <1=> 4 <2=> 6 <3=> 8
-// <4=> 10 <5=> 12 <6=> 14 <7=> 16
-// <8=> 18 <9=> 20 <10=> 22 <11=> 24
-// <12=> 26 <13=> 28 <14=> 30 <15=> 32
-// <16=> 34 <17=> 36 <18=> 38 <19=> 40
-// <20=> 42 <21=> 44 <22=> 46 <23=> 48
-// <24=> 50 <25=> 52 <26=> 54 <27=> 56
-// <28=> 58 <29=> 60 <30=> 62 <31=> 64
-// <o5.5..8> Select Watchdog Oscillator Analog Frequency (Fclkana)
-// <0=> Disabled
-// <1=> 0.5 MHz
-// <2=> 0.8 MHz
-// <3=> 1.1 MHz
-// <4=> 1.4 MHz
-// <5=> 1.6 MHz
-// <6=> 1.8 MHz
-// <7=> 2.0 MHz
-// <8=> 2.2 MHz
-// <9=> 2.4 MHz
-// <10=> 2.6 MHz
-// <11=> 2.7 MHz
-// <12=> 2.9 MHz
-// <13=> 3.1 MHz
-// <14=> 3.2 MHz
-// <15=> 3.4 MHz
-// </e4>
-// <o6> Select Input Clock for sys_pllclkin (Register: SYSPLLCLKSEL)
-// <0=> IRC Oscillator
-// <1=> System Oscillator
-// <2=> WDT Oscillator
-// <3=> Invalid
-// <e7> Use System PLL
-// <i> F_pll = M * F_in
-// <i> F_in must be in the range of 10 MHz to 25 MHz
-// <o8.0..4> M: PLL Multiplier Selection
-// <1-32><#-1>
-// <o8.5..6> P: PLL Divider Selection
-// <0=> 2
-// <1=> 4
-// <2=> 8
-// <3=> 16
-// <o8.7> DIRECT: Direct CCO Clock Output Enable
-// <o8.8> BYPASS: PLL Bypass Enable
-// </e7>
-// <o9> Select Input Clock for Main clock (Register: MAINCLKSEL)
-// <0=> IRC Oscillator
-// <1=> Input Clock to System PLL
-// <2=> WDT Oscillator
-// <3=> System PLL Clock Out
-// </e1>
-// <e10> USB Clock Setup
-// <e11> Use USB PLL
-// <i> F_pll = M * F_in
-// <i> F_in must be in the range of 10 MHz to 25 MHz
-// <o12.0..1> Select Input Clock for usb_pllclkin (Register: USBPLLCLKSEL)
-// <0=> IRC Oscillator
-// <1=> System Oscillator
-// <o13.0..4> M: PLL Multiplier Selection
-// <1-32><#-1>
-// <o13.5..6> P: PLL Divider Selection
-// <0=> 2
-// <1=> 4
-// <2=> 8
-// <3=> 16
-// <o13.7> DIRECT: Direct CCO Clock Output Enable
-// <o13.8> BYPASS: PLL Bypass Enable
-// </e11>
-// </e10>
-// <o14.0..7> System AHB Divider <0-255>
-// <i> 0 = is disabled
-// <o15.0> SYS Clock Enable
-// <o15.1> ROM Clock Enable
-// <o15.2> RAM Clock Enable
-// <o15.3> FLASH1 Clock Enable
-// <o15.4> FLASH2 Clock Enable
-// <o15.5> I2C Clock Enable
-// <o15.6> GPIO Clock Enable
-// <o15.7> CT16B0 Clock Enable
-// <o15.8> CT16B1 Clock Enable
-// <o15.9> CT32B0 Clock Enable
-// <o15.10> CT32B1 Clock Enable
-// <o15.11> SSP Clock Enable
-// <o15.12> UART Clock Enable
-// <o15.13> ADC Clock Enable
-// <o15.14> USB_REG Clock Enable
-// <o15.15> SWDT Clock Enable
-// <o15.16> IOCON Clock Enable
-// </e>
-*/
-#define CLOCK_SETUP 1
-#define SYSCLK_SETUP 1
-#define SYSOSC_SETUP 1
-#define SYSOSCCTRL_Val 0x00000000
-#define WDTOSC_SETUP 0
-#define WDTOSCCTRL_Val 0x000000A0
-#define SYSPLLCLKSEL_Val 0x00000001
-#define SYSPLL_SETUP 1
-#define SYSPLLCTRL_Val 0x00000025
-#define MAINCLKSEL_Val 0x00000003
-
-// ******** Code Red *********
-// * Changed USBCLK_SETUP to 1
-// ***************************
-#define USBCLK_SETUP 1
-#define USBPLL_SETUP 1
-#define USBPLLCLKSEL_Val 0x00000001
-#define USBPLLCTRL_Val 0x00000003
-#define SYSAHBCLKDIV_Val 0x00000001
-#define AHBCLKCTRL_Val 0x0001005F
-
-/*--------------------- Memory Mapping Configuration -------------------------
-//
-// <e> Memory Mapping
-// <o1.0..1> System Memory Remap (Register: SYSMEMREMAP)
-// <0=> Bootloader mapped to address 0
-// <1=> RAM mapped to address 0
-// <2=> Flash mapped to address 0
-// <3=> Flash mapped to address 0
-// </e>
-*/
-#define MEMMAP_SETUP 0
-#define SYSMEMREMAP_Val 0x00000001
-
-/*
-//-------- <<< end of configuration section >>> ------------------------------
-*/
-
-/*----------------------------------------------------------------------------
- Check the register settings
- *----------------------------------------------------------------------------*/
-#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
-#define CHECK_RSVD(val, mask) (val & mask)
-
-/* Clock Configuration -------------------------------------------------------*/
-#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
- #error "SYSOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
- #error "WDTOSCCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
- #error "SYSPLLCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
- #error "SYSPLLCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
- #error "MAINCLKSEL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((USBPLLCLKSEL_Val), 0, 1))
- #error "USBPLLCLKSEL: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((USBPLLCTRL_Val), ~0x000001FF))
- #error "USBPLLCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((USBPLLUEN_Val), ~0x00000001))
- #error "USBPLLUEN: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
- #error "SYSAHBCLKDIV: Value out of range!"
-#endif
-
-#if (CHECK_RSVD((AHBCLKCTRL_Val), ~0x0001FFFF))
- #error "AHBCLKCTRL: Invalid values of reserved bits!"
-#endif
-
-#if (CHECK_RSVD((SYSMEMREMAP_Val), ~0x00000003))
- #error "SYSMEMREMAP: Invalid values of reserved bits!"
-#endif
-
-
-/*----------------------------------------------------------------------------
- DEFINES
- *----------------------------------------------------------------------------*/
-
-/*----------------------------------------------------------------------------
- Define clocks
- *----------------------------------------------------------------------------*/
-#define __XTAL (12000000UL) /* Oscillator frequency */
-#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
-#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
-
-
-#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
-#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
-
-#if (CLOCK_SETUP) /* Clock Setup */
- #if (SYSCLK_SETUP) /* System Clock Setup */
- #if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/
- #if (__FREQSEL == 0)
- #define __WDT_OSC_CLK ( 400000 / __DIVSEL)
- #elif (__FREQSEL == 1)
- #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
- #elif (__FREQSEL == 2)
- #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
- #elif (__FREQSEL == 3)
- #define __WDT_OSC_CLK (1100000 / __DIVSEL)
- #elif (__FREQSEL == 4)
- #define __WDT_OSC_CLK (1400000 / __DIVSEL)
- #elif (__FREQSEL == 5)
- #define __WDT_OSC_CLK (1600000 / __DIVSEL)
- #elif (__FREQSEL == 6)
- #define __WDT_OSC_CLK (1800000 / __DIVSEL)
- #elif (__FREQSEL == 7)
- #define __WDT_OSC_CLK (2000000 / __DIVSEL)
- #elif (__FREQSEL == 8)
- #define __WDT_OSC_CLK (2200000 / __DIVSEL)
- #elif (__FREQSEL == 9)
- #define __WDT_OSC_CLK (2400000 / __DIVSEL)
- #elif (__FREQSEL == 10)
- #define __WDT_OSC_CLK (2600000 / __DIVSEL)
- #elif (__FREQSEL == 11)
- #define __WDT_OSC_CLK (2700000 / __DIVSEL)
- #elif (__FREQSEL == 12)
- #define __WDT_OSC_CLK (2900000 / __DIVSEL)
- #elif (__FREQSEL == 13)
- #define __WDT_OSC_CLK (3100000 / __DIVSEL)
- #elif (__FREQSEL == 14)
- #define __WDT_OSC_CLK (3200000 / __DIVSEL)
- #else
- #define __WDT_OSC_CLK (3400000 / __DIVSEL)
- #endif
- #else
- #define __WDT_OSC_CLK (1600000 / 2)
- #endif // WDTOSC_SETUP
-
- /* sys_pllclkin calculation */
- #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
- #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
- #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
- #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
- #elif ((SYSPLLCLKSEL_Val & 0x03) == 2)
- #define __SYS_PLLCLKIN (__WDT_OSC_CLK)
- #else
- #define __SYS_PLLCLKIN (0)
- #endif
-
- #if (SYSPLL_SETUP) /* System PLL Setup */
- #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
- #else
- #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * (1))
- #endif // SYSPLL_SETUP
-
- /* main clock calculation */
- #if ((MAINCLKSEL_Val & 0x03) == 0)
- #define __MAIN_CLOCK (__IRC_OSC_CLK)
- #elif ((MAINCLKSEL_Val & 0x03) == 1)
- #define __MAIN_CLOCK (__SYS_PLLCLKIN)
- #elif ((MAINCLKSEL_Val & 0x03) == 2)
- #define __MAIN_CLOCK (__WDT_OSC_CLK)
- #elif ((MAINCLKSEL_Val & 0x03) == 3)
- #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
- #else
- #define __MAIN_CLOCK (0)
- #endif
-
- #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
-
- #else // SYSCLK_SETUP
- #if (SYSAHBCLKDIV_Val == 0)
- #define __SYSTEM_CLOCK (0)
- #else
- #define __SYSTEM_CLOCK (__XTAL / SYSAHBCLKDIV_Val)
- #endif
- #endif // SYSCLK_SETUP
-
-#else
- #define __SYSTEM_CLOCK (__XTAL)
-#endif // CLOCK_SETUP
-
-
-/*----------------------------------------------------------------------------
- Clock Variable definitions
- *----------------------------------------------------------------------------*/
-uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
-
-
-/*----------------------------------------------------------------------------
- Clock functions
- *----------------------------------------------------------------------------*/
-void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
-{
- uint32_t wdt_osc = 0;
-
- /* Determine clock frequency according to clock register values */
- switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) {
- case 0: wdt_osc = 400000; break;
- case 1: wdt_osc = 500000; break;
- case 2: wdt_osc = 800000; break;
- case 3: wdt_osc = 1100000; break;
- case 4: wdt_osc = 1400000; break;
- case 5: wdt_osc = 1600000; break;
- case 6: wdt_osc = 1800000; break;
- case 7: wdt_osc = 2000000; break;
- case 8: wdt_osc = 2200000; break;
- case 9: wdt_osc = 2400000; break;
- case 10: wdt_osc = 2600000; break;
- case 11: wdt_osc = 2700000; break;
- case 12: wdt_osc = 2900000; break;
- case 13: wdt_osc = 3100000; break;
- case 14: wdt_osc = 3200000; break;
- case 15: wdt_osc = 3400000; break;
- }
- wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2;
-
- switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
- case 0: /* Internal RC oscillator */
- SystemCoreClock = __IRC_OSC_CLK;
- break;
- case 1: /* Input Clock to System PLL */
- switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
- case 0: /* Internal RC oscillator */
- SystemCoreClock = __IRC_OSC_CLK;
- break;
- case 1: /* System oscillator */
- SystemCoreClock = __SYS_OSC_CLK;
- break;
- case 2: /* WDT Oscillator */
- SystemCoreClock = wdt_osc;
- break;
- case 3: /* Reserved */
- SystemCoreClock = 0;
- break;
- }
- break;
- case 2: /* WDT Oscillator */
- SystemCoreClock = wdt_osc;
- break;
- case 3: /* System PLL Clock Out */
- switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
- case 0: /* Internal RC oscillator */
- if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
- SystemCoreClock = __IRC_OSC_CLK;
- } else {
- SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
- }
- break;
- case 1: /* System oscillator */
- if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
- SystemCoreClock = __SYS_OSC_CLK;
- } else {
- SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
- }
- break;
- case 2: /* WDT Oscillator */
- if (LPC_SYSCON->SYSPLLCTRL & 0x180) {
- SystemCoreClock = wdt_osc;
- } else {
- SystemCoreClock = wdt_osc * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
- }
- break;
- case 3: /* Reserved */
- SystemCoreClock = 0;
- break;
- }
- break;
- }
-
- SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
-
-}
-
-/**
- * Initialize the system
- *
- * @param none
- * @return none
- *
- * @brief Setup the microcontroller system.
- * Initialize the System.
- */
-void SystemInit (void)
-{
-#if (CLOCK_SETUP) /* Clock Setup */
-#if (SYSCLK_SETUP) /* System Clock Setup */
-#if (SYSOSC_SETUP) /* System Oscillator Setup */
- uint32_t i;
-
- LPC_SYSCON->PDRUNCFG &= ~(1 << 5); /* Power-up System Osc */
- LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val;
- for (i = 0; i < 200; i++) __NOP();
- LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */
- LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */
- LPC_SYSCON->SYSPLLCLKUEN = 0x00; /* Toggle Update Register */
- LPC_SYSCON->SYSPLLCLKUEN = 0x01;
- while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */
-#if (SYSPLL_SETUP) /* System PLL Setup */
- LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val;
- LPC_SYSCON->PDRUNCFG &= ~(1 << 7); /* Power-up SYSPLL */
- while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */
-#endif
-#endif
-#if (WDTOSC_SETUP) /* Watchdog Oscillator Setup*/
- LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val;
- LPC_SYSCON->PDRUNCFG &= ~(1 << 6); /* Power-up WDT Clock */
-#endif
- LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */
- LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */
- LPC_SYSCON->MAINCLKUEN = 0x00; /* Toggle Update Register */
- LPC_SYSCON->MAINCLKUEN = 0x01;
- while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */
-#endif
-
-#if (USBCLK_SETUP) /* USB Clock Setup */
- LPC_SYSCON->PDRUNCFG &= ~(1 << 10); /* Power-up USB PHY */
-#if (USBPLL_SETUP) /* USB PLL Setup */
- LPC_SYSCON->PDRUNCFG &= ~(1 << 8); /* Power-up USB PLL */
- LPC_SYSCON->USBPLLCLKSEL = USBPLLCLKSEL_Val; /* Select PLL Input */
- LPC_SYSCON->USBPLLCLKUEN = 0x01; /* Update Clock Source */
- LPC_SYSCON->USBPLLCLKUEN = 0x00; /* Toggle Update Register */
- LPC_SYSCON->USBPLLCLKUEN = 0x01;
- while (!(LPC_SYSCON->USBPLLCLKUEN & 0x01)); /* Wait Until Updated */
- LPC_SYSCON->USBPLLCTRL = USBPLLCTRL_Val;
- while (!(LPC_SYSCON->USBPLLSTAT & 0x01)); /* Wait Until PLL Locked */
- LPC_SYSCON->USBCLKSEL = 0x00; /* Select USB PLL */
-#else
- LPC_SYSCON->USBCLKSEL = 0x01; /* Select Main Clock */
-#endif
-#else
- LPC_SYSCON->PDRUNCFG |= (1 << 10); /* Power-down USB PHY */
- LPC_SYSCON->PDRUNCFG |= (1 << 8); /* Power-down USB PLL */
-#endif
-
- LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val;
- LPC_SYSCON->SYSAHBCLKCTRL = AHBCLKCTRL_Val;
-#endif
-
-
-#if (MEMMAP_SETUP || MEMMAP_INIT) /* Memory Mapping Setup */
- LPC_SYSCON->SYSMEMREMAP = SYSMEMREMAP_Val;
-#endif
-}
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