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/*
* spreadspace avr utils
*
*
* Copyright (C) 2013-2015 Christian Pointner <equinox@spreadspace.org>
*
* This file is part of spreadspace avr utils.
*
* spreadspace avr utils is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* any later version.
*
* spreadspace avr utils is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with spreadspace avr utils. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef SPREADAVR_CC1101_defines_h_INCLUDED
#define SPREADAVR_CC1101_defines_h_INCLUDED
//// header byte
#define CC1101_HEADER_READ 0x80
#define CC1101_HEADER_WRITE 0x00
#define CC1101_HEADER_BURST 0x40
#define CC1101_HEADER_READONLY 0xC0
#define CC1101_HEADER_COMMAND 0x00
//read/write config registers:
#define CC1101_REG_RW_IOCFG2 0x00
#define CC1101_REG_RW_IOCFG1 0x01
#define CC1101_REG_RW_IOCFG0 0x02
#define CC1101_REG_RW_FIFOTHR 0x03
#define CC1101_REG_RW_SYNC1 0x04
#define CC1101_REG_RW_SYNC0 0x05
#define CC1101_REG_RW_PKTLEN 0x06
#define CC1101_REG_RW_PKTCTRL1 0x07
#define CC1101_REG_RW_PKTCTRL0 0x08
#define CC1101_REG_RW_ADDR 0x09
#define CC1101_REG_RW_CHANNR 0x0A
#define CC1101_REG_RW_FSCTRL1 0x0B
#define CC1101_REG_RW_FSCTRL0 0x0C
#define CC1101_REG_RW_FREQ2 0x0D
#define CC1101_REG_RW_FREQ1 0x0E
#define CC1101_REG_RW_FREQ0 0x0F
#define CC1101_REG_RW_MDMCFG4 0x10
#define CC1101_REG_RW_MDMCFG3 0x11
#define CC1101_REG_RW_MDMCFG2 0x12
#define CC1101_REG_RW_MDMCFG1 0x13
#define CC1101_REG_RW_MDMCFG0 0x14
#define CC1101_REG_RW_DEVIATN 0x15
#define CC1101_REG_RW_MCSM2 0x16
#define CC1101_REG_RW_MCSM1 0x17
#define CC1101_REG_RW_MCSM0 0x18
#define CC1101_REG_RW_FOCCFG 0x19
#define CC1101_REG_RW_BSCFG 0x1A
#define CC1101_REG_RW_AGCCTRL2 0x1B
#define CC1101_REG_RW_AGCCTRL1 0x1C
#define CC1101_REG_RW_AGCCTRL0 0x1D
#define CC1101_REG_RW_WOREVT1 0x1E
#define CC1101_REG_RW_WOREVT0 0x1F
#define CC1101_REG_RW_WORCTRL 0x20
#define CC1101_REG_RW_FREND1 0x21
#define CC1101_REG_RW_FREND0 0x22
#define CC1101_REG_RW_FSCAL3 0x23
#define CC1101_REG_RW_FSCAL2 0x24
#define CC1101_REG_RW_FSCAL1 0x25
#define CC1101_REG_RW_FSCAL0 0x26
#define CC1101_REG_RW_RCCTRL1 0x27
#define CC1101_REG_RW_RCCTRL0 0x28
#define CC1101_REG_RW_FSTEST 0x29
#define CC1101_REG_RW_PTEST 0x2A
#define CC1101_REG_RW_AGCTEST 0x2B
#define CC1101_REG_RW_TEST2 0x2C
#define CC1101_REG_RW_TEST1 0x2D
#define CC1101_REG_RW_TEST0 0x2E
#define CC1101_REG_RW_MIN 0x00
#define CC1101_REG_RW_MAX 0x2E
//read-only status registers:
#define CC1101_REG_RO_PARTNUM 0x30
#define CC1101_REG_RO_VERSION 0x31
#define CC1101_REG_RO_FREQUEST 0x32
#define CC1101_REG_RO_LQI 0x33
#define CC1101_REG_RO_RSSI 0x34
#define CC1101_REG_RO_MARCSTATE 0x35
#define CC1101_REG_RO_WORTIME1 0x36
#define CC1101_REG_RO_WORTIME0 0x37
#define CC1101_REG_RO_PKTSTATUS 0x38
#define CC1101_REG_RO_VCO_VC_DAC 0x39
#define CC1101_REG_RO_TXBYTES 0x3A
#define CC1101_REG_RO_RXBYTES 0x3B
#define CC1101_REG_RO_RCCTRL1_STATUS 0x3C
#define CC1101_REG_RO_RCCTRL0_STATUS 0x3D
#define CC1101_REG_RO_MIN 0x30
#define CC1101_REG_RO_MAX 0x3D
//commands:
#define CC1101_CMD_SRES 0x30
#define CC1101_CMD_SFSTXON 0x31
#define CC1101_CMD_SXOFF 0x32
#define CC1101_CMD_SCAL 0x33
#define CC1101_CMD_SRX 0x34
#define CC1101_CMD_STX 0x35
#define CC1101_CMD_SIDLE 0x36
#define CC1101_CMD_SWOR 0x38
#define CC1101_CMD_SPWD 0x39
#define CC1101_CMD_SFRX 0x3A
#define CC1101_CMD_SFTX 0x3B
#define CC1101_CMD_SWORRST 0x3C
#define CC1101_CMD_SNOP 0x3D
#define CC1101_CMD_MIN 0x30
#define CC1101_CMD_MAX 0x3D
//power amplifier table
#define CC1101_REG_PATABLE 0x3E
#define CC1101_PATABLE_SIZE 8
//data FIFOs
#define CC1101_REG_FIFO 0x3F
#define CC1101_FIFO_MAX_LEN 64
#define CC1101_ADDR_MAX 0x3F
////status byte:
#define CC1101_STATUS_CHIP_NOT_RDY(x) (x & 0b10000000)
#define CC1101_STATUS_IDLE(x) ((x & 0b01110000) == 0b00000000)
#define CC1101_STATUS_RXMODE(x) ((x & 0b01110000) == 0b00010000)
#define CC1101_STATUS_TXMODE(x) ((x & 0b01110000) == 0b00100000)
#define CC1101_STATUS_FSTXON(x) ((x & 0b01110000) == 0b00110000)
#define CC1101_STATUS_CALIBRATE(x) ((x & 0b01110000) == 0b01000000)
#define CC1101_STATUS_SETTLING(x) ((x & 0b01110000) == 0b01010000)
#define CC1101_STATUS_RXFIFO_OVERFLOW(x) ((x & 0b01110000) == 0b01100000)
#define CC1101_STATUS_TXFIFO_OVERFLOW(x) ((x & 0b01110000) == 0b01110000)
#define CC1101_STATUS_FIFO_BYTES_AVAILABLE(x) (x & 0b00001111)
#define CC1101_MARCSTATE_SLEEP 0x00
#define CC1101_MARCSTATE_IDLE 0x01
#define CC1101_MARCSTATE_XOFF 0x02
#define CC1101_MARCSTATE_VCOON_MC 0x03
#define CC1101_MARCSTATE_REGON_MC 0x04
#define CC1101_MARCSTATE_MANCAL 0x05
#define CC1101_MARCSTATE_VCOON 0x06
#define CC1101_MARCSTATE_REGON 0x07
#define CC1101_MARCSTATE_STARTCAL 0x08
#define CC1101_MARCSTATE_BWBOOST 0x09
#define CC1101_MARCSTATE_FS_LOCK 0x0A
#define CC1101_MARCSTATE_IFADCON 0x0B
#define CC1101_MARCSTATE_ENDCAL 0x0C
#define CC1101_MARCSTATE_RX 0x0D
#define CC1101_MARCSTATE_RX_END 0x0E
#define CC1101_MARCSTATE_RX_RST 0x0F
#define CC1101_MARCSTATE_TXRX_SWITCH 0x10
#define CC1101_MARCSTATE_RXFIFO_OVERFLOW 0x11
#define CC1101_MARCSTATE_FSTXON 0x12
#define CC1101_MARCSTATE_TX 0x13
#define CC1101_MARCSTATE_TX_END 0x14
#define CC1101_MARCSTATE_RXTX_SWITCH 0x15
#define CC1101_MARCSTATE_TXFIFO_UNDERFLOW 0x16
#define CC1101_GDO_CFG_3STATE 0x2E
//register masks
#define CC1101_REG_RW_IOCFG2_MASK 0x7F
#define CC1101_REG_RW_IOCFG1_MASK 0xFF
#define CC1101_REG_RW_IOCFG0_MASK 0xFF
#define CC1101_REG_RW_FIFOTHR_MASK 0x7F
#define CC1101_REG_RW_SYNC1_MASK 0xFF
#define CC1101_REG_RW_SYNC0_MASK 0xFF
#define CC1101_REG_RW_PKTLEN_MASK 0xFF
#define CC1101_REG_RW_PKTCTRL1_MASK 0xEF
#define CC1101_REG_RW_PKTCTRL0_MASK 0x77
#define CC1101_REG_RW_ADDR_MASK 0xFF
#define CC1101_REG_RW_CHANNR_MASK 0xFF
#define CC1101_REG_RW_FSCTRL1_MASK 0x1F
#define CC1101_REG_RW_FSCTRL0_MASK 0xFF
#define CC1101_REG_RW_FREQ2_MASK 0x3F
#define CC1101_REG_RW_FREQ1_MASK 0xFF
#define CC1101_REG_RW_FREQ0_MASK 0xFF
#define CC1101_REG_RW_MDMCFG4_MASK 0xFF
#define CC1101_REG_RW_MDMCFG3_MASK 0xFF
#define CC1101_REG_RW_MDMCFG2_MASK 0xFF
#define CC1101_REG_RW_MDMCFG1_MASK 0xF3
#define CC1101_REG_RW_MDMCFG0_MASK 0xFF
#define CC1101_REG_RW_DEVIATN_MASK 0x77
#define CC1101_REG_RW_MCSM2_MASK 0x1F
#define CC1101_REG_RW_MCSM1_MASK 0x3F
#define CC1101_REG_RW_MCSM0_MASK 0x3F
#define CC1101_REG_RW_FOCCFG_MASK 0x3F
#define CC1101_REG_RW_BSCFG_MASK 0xFF
#define CC1101_REG_RW_AGCCTRL2_MASK 0xFF
#define CC1101_REG_RW_AGCCTRL1_MASK 0x7F
#define CC1101_REG_RW_AGCCTRL0_MASK 0xFF
#define CC1101_REG_RW_WOREVT1_MASK 0xFF
#define CC1101_REG_RW_WOREVT0_MASK 0xFF
#define CC1101_REG_RW_WORCTRL_MASK 0xFB
#define CC1101_REG_RW_FREND1_MASK 0xFF
#define CC1101_REG_RW_FREND0_MASK 0x37
#define CC1101_REG_RW_FSCAL3_MASK 0xFF
#define CC1101_REG_RW_FSCAL2_MASK 0x3F
#define CC1101_REG_RW_FSCAL1_MASK 0x3F
#define CC1101_REG_RW_FSCAL0_MASK 0x7F
#define CC1101_REG_RW_RCCTRL1_MASK 0x7F
#define CC1101_REG_RW_RCCTRL0_MASK 0x7F
#define CC1101_REG_RW_FSTEST_MASK 0xFF
#define CC1101_REG_RW_PTEST_MASK 0xFF
#define CC1101_REG_RW_AGCTEST_MASK 0xFF
#define CC1101_REG_RW_TEST2_MASK 0xFF
#define CC1101_REG_RW_TEST1_MASK 0xFF
#define CC1101_REG_RW_TEST0_MASK 0xFF
#define CC1101_REG_RO_PARTNUM_MASK 0xFF
#define CC1101_REG_RO_VERSION_MASK 0xFF
#define CC1101_REG_RO_FREQUEST_MASK 0xFF
#define CC1101_REG_RO_LQI_MASK 0xFF
#define CC1101_REG_RO_RSSI_MASK 0xFF
#define CC1101_REG_RO_MARCSTATE_MASK 0x1F
#define CC1101_REG_RO_WORTIME1_MASK 0xFF
#define CC1101_REG_RO_WORTIME0_MASK 0xFF
#define CC1101_REG_RO_PKTSTATUS_MASK 0xFF
#define CC1101_REG_RO_VCO_VC_DAC_MASK 0xFF
#define CC1101_REG_RO_TXBYTES_MASK 0xFF
#define CC1101_REG_RO_RXBYTES_MASK 0xFF
#define CC1101_REG_RO_RCCTRL1_STATUS_MASK 0x7F
#define CC1101_REG_RO_RCCTRL0_STATUS_MASK 0x7F
#endif
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