From 7c5c20839c20417ae4929cfdee80da2d5633aa72 Mon Sep 17 00:00:00 2001 From: Christian Pointner Date: Wed, 18 Feb 2015 21:19:26 +0100 Subject: hhd70: added interface for direct register access --- software/avr.lib/cc1101.c | 313 ++++++++++++++++++++++++++++++++++++-- software/avr.lib/cc1101.h | 71 ++++++++- software/avr.lib/cc1101_defines.h | 2 + 3 files changed, 368 insertions(+), 18 deletions(-) diff --git a/software/avr.lib/cc1101.c b/software/avr.lib/cc1101.c index 5c9f2f8..7ad87ea 100644 --- a/software/avr.lib/cc1101.c +++ b/software/avr.lib/cc1101.c @@ -104,7 +104,19 @@ void cc1101_init(cc1101_driver_conf_t conf) void cc1101_reg_init(void) { - // TODO: init register depending on mode beacon vs. data + // TODO: this is hack for Beacon mode... + cc1101_spi_write_register(CC1101_REG_RW_IOCFG0, CC1101_GDO_CFG_3STATE); + cc1101_spi_write_register(CC1101_REG_RW_IOCFG1, CC1101_GDO_CFG_3STATE); + cc1101_spi_write_register(CC1101_REG_RW_IOCFG2, CC1101_GDO_CFG_3STATE); + + cc1101_spi_write_register(CC1101_REG_RW_PKTCTRL0, 0b0000110001); //crc disabled; asynchronous serial input on GDO0 + cc1101_spi_write_register(CC1101_REG_RW_FSCTRL1,0x06); //Frequency Synthesizer Control + cc1101_spi_write_register(CC1101_REG_RW_MDMCFG4,0xF5); //Modem Configuration + cc1101_spi_write_register(CC1101_REG_RW_MDMCFG3,0x43); //Modem Configuration + cc1101_spi_write_register(CC1101_REG_RW_MDMCFG2,0x30); //Modem Configuration + cc1101_spi_write_register(CC1101_REG_RW_MDMCFG1,0x00); //Modem Configuration + cc1101_spi_write_register(CC1101_REG_RW_MCSM0,0x18); //Main Radio Control State Machine Configuration + cc1101_spi_write_register(CC1101_REG_RW_FREND0,0x11); //Front End TX Configuration // PA_POWER[2:0] = 1 } void cc1101_soft_reset(void) @@ -204,29 +216,275 @@ cc1101_state_t cc1101_get_state(void) return cc1101_marcstate_to_state(cc1101_spi_read_register(CC1101_REG_RO_MARCSTATE)); } -void cc1101_set_freq_hz(uint32_t hz) +uint8_t cc1101_get_iocfg0(void) { - uint32_t freq = (uint32_t)((float)hz / drv.freq_corr); - if(freq <= 0x3FFFFF) + return 0xFF; +} - // TODO: this is only allowed in idle mode - cc1101_spi_write_register(CC1101_REG_RW_FREQ0, freq & 0xFF); - cc1101_spi_write_register(CC1101_REG_RW_FREQ1, (freq >> 8) & 0xFF); - cc1101_spi_write_register(CC1101_REG_RW_FREQ2, (freq >> 16) & 0x3F); +void cc1101_set_iocfg0(uint8_t iocfg) +{ } -uint32_t cc1101_get_freq_hz(void) +uint8_t cc1101_get_iocfg1(void) { - uint32_t freq = 0; - freq = cc1101_spi_read_register(CC1101_REG_RW_FREQ2) & 0x3F; - freq = freq << 8; - freq |= cc1101_spi_read_register(CC1101_REG_RW_FREQ1); - freq = freq << 8; - freq |= cc1101_spi_read_register(CC1101_REG_RW_FREQ0); + return 0xFF; +} - return (uint32_t)((float)freq * drv.freq_corr); +void cc1101_set_iocfg1(uint8_t iocfg) +{ +} + +uint8_t cc1101_get_iocfg2(void) +{ + return 0xFF; +} + +void cc1101_set_iocfg2(uint8_t iocfg) +{ +} + + +uint8_t cc1101_get_fifothr(void) +{ + return 0xFF; +} + +void cc1101_set_fifothr(uint8_t fifothr) +{ +} + + +uint16_t cc1101_get_sync(void) +{ + return 0xFFFF; +} + +void cc1101_set_sync(uint16_t sync) +{ +} + +uint8_t cc1101_get_pktlen(void) +{ + return 0xFF; +} + +void cc1101_set_pktlen(uint8_t len) +{ +} + +uint16_t cc1101_get_pktctrl(void) +{ + return 0xFF; +} + +void cc1101_set_pktctrl(uint16_t ctrl) +{ +} + +uint8_t cc1101_get_addr(void) +{ + return 0xFF; +} + +void cc1101_set_addr(uint8_t addr) +{ +} + + +uint8_t cc1101_get_channr(void) +{ + return 0xFF; +} + +void cc1101_set_channr(uint8_t nr) +{ +} + +uint8_t cc1101_get_iffreq(void) +{ + return 0xFF; +} + +void cc1101_set_iffreq(uint8_t iffreq) +{ +} + +uint8_t cc1101_get_freq_offset(void) +{ + return 0xFF; +} + +void cc1101_set_freq_offset(uint8_t freqoff) +{ +} + +uint32_t cc1101_get_freq(void) +{ + return 0x3FFFFF; +} + +void cc1101_set_freq(uint32_t freq) +{ +} + +uint8_t cc1101_get_deviatn(void) +{ + return 0xFF; +} + +void cc1101_set_deviatn(uint8_t dev) +{ +} + +uint64_t cc1101_get_modemcfg(void) +{ + return 0xFFFFFFFFFFFFFFFF; +} + +void cc1101_set_modemcfg(uint64_t cfg) +{ +} + + +uint32_t cc1101_get_mcsm(void) +{ + return 0xFFFFFFFF; +} + +void cc1101_set_mcsm(uint32_t cfg) +{ +} + + +uint8_t cc1101_get_foccfg(void) +{ + return 0xFF; +} + +void cc1101_set_foccfg(uint8_t cfg) +{ +} + +uint8_t cc1101_get_bscfg(void) +{ + return 0xFF; +} + +void cc1101_set_bscfg(uint8_t cfg) +{ +} + +uint32_t cc1101_get_agcctrl(void) +{ + return 0xFFFFFFFF; +} + +void cc1101_set_agcctrl(uint32_t ctrl) +{ +} + +uint16_t cc1101_get_worevt(void) +{ + return 0xFFFF; +} + +void cc1101_set_worevt(uint16_t timeout) +{ +} + +uint8_t cc1101_get_worctrl(void) +{ + return 0xFF; +} + +void cc1101_set_worctrl(uint8_t ctrl) +{ +} + + +uint16_t cc1101_get_frend(void) +{ + return 0xFFFF; +} + +void cc1101_set_frend(uint16_t cfg) +{ +} + +uint32_t cc1101_get_fscal(void) +{ + return 0xFFFFFFFF; +} + +void cc1101_set_fscal(uint32_t cal) +{ +} + +uint16_t cc1101_get_rcctrl(void) +{ + return 0xFFFF; +} + +void cc1101_set_rcctrl(uint16_t ctrl) +{ +} + + +uint8_t cc1101_get_fstest(void) +{ + return 0xFF; +} + +void cc1101_set_fstest(uint8_t test) +{ +} + +uint8_t cc1101_get_pstest(void) +{ + return 0xFF; +} + +void cc1101_set_pstest(uint8_t test) +{ +} + +uint8_t cc1101_get_agctest(void) +{ + return 0xFF; +} + +void cc1101_set_agctest(uint8_t test) +{ +} + +uint8_t cc1101_get_test0(void) +{ + return 0xFF; } +void cc1101_set_test0(uint8_t test) +{ +} + +uint8_t cc1101_get_test1(void) +{ + return 0xFF; +} + +void cc1101_set_test1(uint8_t test) +{ +} + +uint8_t cc1101_get_test2(void) +{ + return 0xFF; +} + +void cc1101_set_test2(uint8_t test) +{ +} + + uint8_t cc1101_get_partnum(void) { return cc1101_spi_read_register(CC1101_REG_RO_PARTNUM); @@ -370,3 +628,26 @@ void cc1101_dump_register(void) } printf("\r\n"); } + +uint32_t cc1101_get_freq_hz(void) +{ + uint32_t freq = 0; + freq = cc1101_spi_read_register(CC1101_REG_RW_FREQ2) & 0x3F; + freq = freq << 8; + freq |= cc1101_spi_read_register(CC1101_REG_RW_FREQ1); + freq = freq << 8; + freq |= cc1101_spi_read_register(CC1101_REG_RW_FREQ0); + + return (uint32_t)((float)freq * drv.freq_corr); +} + +void cc1101_set_freq_hz(uint32_t hz) +{ + uint32_t freq = (uint32_t)((float)hz / drv.freq_corr); + if(freq <= 0x3FFFFF) + + // TODO: this is only allowed in idle mode + cc1101_spi_write_register(CC1101_REG_RW_FREQ0, freq & 0xFF); + cc1101_spi_write_register(CC1101_REG_RW_FREQ1, (freq >> 8) & 0xFF); + cc1101_spi_write_register(CC1101_REG_RW_FREQ2, (freq >> 16) & 0x3F); +} diff --git a/software/avr.lib/cc1101.h b/software/avr.lib/cc1101.h index ffb886e..ec676e4 100644 --- a/software/avr.lib/cc1101.h +++ b/software/avr.lib/cc1101.h @@ -52,8 +52,71 @@ void cc1101_rx(void); void cc1101_tx(void); cc1101_state_t cc1101_get_state(void); -void cc1101_set_freq_hz(uint32_t hz); -uint32_t cc1101_get_freq_hz(void); +uint8_t cc1101_get_iocfg0(void); +void cc1101_set_iocfg0(uint8_t iocfg); +uint8_t cc1101_get_iocfg1(void); +void cc1101_set_iocfg1(uint8_t iocfg); +uint8_t cc1101_get_iocfg2(void); +void cc1101_set_iocfg2(uint8_t iocfg); + +uint8_t cc1101_get_fifothr(void); +void cc1101_set_fifothr(uint8_t fifothr); + +uint16_t cc1101_get_sync(void); +void cc1101_set_sync(uint16_t sync); +uint8_t cc1101_get_pktlen(void); +void cc1101_set_pktlen(uint8_t len); +uint16_t cc1101_get_pktctrl(void); +void cc1101_set_pktctrl(uint16_t ctrl); +uint8_t cc1101_get_addr(void); +void cc1101_set_addr(uint8_t addr); + +uint8_t cc1101_get_channr(void); +void cc1101_set_channr(uint8_t nr); +uint8_t cc1101_get_iffreq(void); +void cc1101_set_iffreq(uint8_t iffreq); +uint8_t cc1101_get_freq_offset(void); +void cc1101_set_freq_offset(uint8_t freqoff); +uint32_t cc1101_get_freq(void); +void cc1101_set_freq(uint32_t freq); +uint8_t cc1101_get_deviatn(void); +void cc1101_set_deviatn(uint8_t dev); +uint64_t cc1101_get_modemcfg(void); +void cc1101_set_modemcfg(uint64_t cfg); + +uint32_t cc1101_get_mcsm(void); +void cc1101_set_mcsm(uint32_t cfg); + +uint8_t cc1101_get_foccfg(void); +void cc1101_set_foccfg(uint8_t cfg); +uint8_t cc1101_get_bscfg(void); +void cc1101_set_bscfg(uint8_t cfg); +uint32_t cc1101_get_agcctrl(void); +void cc1101_set_agcctrl(uint32_t ctrl); +uint16_t cc1101_get_worevt(void); +void cc1101_set_worevt(uint16_t timeout); +uint8_t cc1101_get_worctrl(void); +void cc1101_set_worctrl(uint8_t ctrl); + +uint16_t cc1101_get_frend(void); +void cc1101_set_frend(uint16_t cfg); +uint32_t cc1101_get_fscal(void); +void cc1101_set_fscal(uint32_t cal); +uint16_t cc1101_get_rcctrl(void); +void cc1101_set_rcctrl(uint16_t ctrl); + +uint8_t cc1101_get_fstest(void); +void cc1101_set_fstest(uint8_t test); +uint8_t cc1101_get_pstest(void); +void cc1101_set_pstest(uint8_t test); +uint8_t cc1101_get_agctest(void); +void cc1101_set_agctest(uint8_t test); +uint8_t cc1101_get_test0(void); +void cc1101_set_test0(uint8_t test); +uint8_t cc1101_get_test1(void); +void cc1101_set_test1(uint8_t test); +uint8_t cc1101_get_test2(void); +void cc1101_set_test2(uint8_t test); uint8_t cc1101_get_partnum(void); uint8_t cc1101_get_chip_version(void); @@ -67,4 +130,8 @@ uint8_t cc1101_get_rx_bytes(void); void cc1101_dump_register(void); + +uint32_t cc1101_get_freq_hz(void); +void cc1101_set_freq_hz(uint32_t hz); + #endif diff --git a/software/avr.lib/cc1101_defines.h b/software/avr.lib/cc1101_defines.h index a257e75..76a632b 100644 --- a/software/avr.lib/cc1101_defines.h +++ b/software/avr.lib/cc1101_defines.h @@ -167,4 +167,6 @@ #define CC1101_MARCSTATE_RXTX_SWITCH 0x15 #define CC1101_MARCSTATE_TXFIFO_UNDERFLOW 0x16 +#define CC1101_GDO_CFG_3STATE 0x2E + #endif -- cgit v1.2.3