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authorChristian Pointner <equinox@spreadspace.org>2015-03-03 01:17:13 +0100
committerChristian Pointner <equinox@spreadspace.org>2015-03-03 01:17:13 +0100
commitf7ca393b8da16c479e895387d59563507ba708e9 (patch)
tree2dc10834ecf16ff61d28b8fe84d51326934ad489
parentsplit up modemcfg into 2 smaller pieces (diff)
multi byte register reads use burst transfer now
-rw-r--r--lib/cc1101.c92
1 files changed, 64 insertions, 28 deletions
diff --git a/lib/cc1101.c b/lib/cc1101.c
index 091b9e4..0bf604b 100644
--- a/lib/cc1101.c
+++ b/lib/cc1101.c
@@ -351,9 +351,12 @@ void cc1101_set_fifothr(uint8_t fifothr)
uint16_t cc1101_get_sync(void)
{
- uint16_t sync = cc1101_spi_read_register(CC1101_REG_RW_SYNC1) & CC1101_REG_RW_SYNC1_MASK;
+ uint8_t data[2];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_SYNC1, data, 2);
+
+ uint16_t sync = data[0] & CC1101_REG_RW_SYNC1_MASK;
sync = sync << 8;
- sync |= cc1101_spi_read_register(CC1101_REG_RW_SYNC0) & CC1101_REG_RW_SYNC0_MASK;
+ sync |= data[1] & CC1101_REG_RW_SYNC0_MASK;
return sync;
}
@@ -376,9 +379,12 @@ void cc1101_set_pktlen(uint8_t len)
uint16_t cc1101_get_pktctrl(void)
{
- uint16_t ctrl = cc1101_spi_read_register(CC1101_REG_RW_PKTCTRL1) & CC1101_REG_RW_PKTCTRL1_MASK;
+ uint8_t data[2];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_PKTCTRL1, data, 2);
+
+ uint16_t ctrl = data[0] & CC1101_REG_RW_PKTCTRL1_MASK;
ctrl = ctrl << 8;
- ctrl |= cc1101_spi_read_register(CC1101_REG_RW_PKTCTRL0) & CC1101_REG_RW_PKTCTRL0_MASK;
+ ctrl |= data[1] & CC1101_REG_RW_PKTCTRL0_MASK;
return ctrl;
}
@@ -432,11 +438,14 @@ void cc1101_set_freq_offset(uint8_t freqoff)
uint32_t cc1101_get_freq(void)
{
- uint32_t freq = cc1101_spi_read_register(CC1101_REG_RW_FREQ2) & CC1101_REG_RW_FREQ2_MASK;
+ uint8_t data[3];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_FREQ2, data, 3);
+
+ uint32_t freq = data[0] & CC1101_REG_RW_FREQ2_MASK;
freq = freq << 8;
- freq |= cc1101_spi_read_register(CC1101_REG_RW_FREQ1) & CC1101_REG_RW_FREQ1_MASK;
+ freq |= data[1] & CC1101_REG_RW_FREQ1_MASK;
freq = freq << 8;
- freq |= cc1101_spi_read_register(CC1101_REG_RW_FREQ0) & CC1101_REG_RW_FREQ0_MASK;
+ freq |= data[2] & CC1101_REG_RW_FREQ0_MASK;
return freq;
}
@@ -451,11 +460,14 @@ void cc1101_set_freq(uint32_t freq)
uint32_t cc1101_get_modemcfg(void)
{
- uint32_t cfg = cc1101_spi_read_register(CC1101_REG_RW_MDMCFG2) & CC1101_REG_RW_MDMCFG2_MASK;
+ uint8_t data[3];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_MDMCFG2, data, 3);
+
+ uint32_t cfg = data[0] & CC1101_REG_RW_MDMCFG2_MASK;
cfg = cfg << 8;
- cfg |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG1) & CC1101_REG_RW_MDMCFG1_MASK;
+ cfg |= data[1] & CC1101_REG_RW_MDMCFG1_MASK;
cfg = cfg << 8;
- cfg |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG0) & CC1101_REG_RW_MDMCFG0_MASK;
+ cfg |= data[2] & CC1101_REG_RW_MDMCFG0_MASK;
return cfg;
}
@@ -470,9 +482,12 @@ void cc1101_set_modemcfg(uint32_t cfg)
uint16_t cc1101_get_drate_bw(void)
{
- uint16_t cfg = cc1101_spi_read_register(CC1101_REG_RW_MDMCFG4) & CC1101_REG_RW_MDMCFG4_MASK;
+ uint8_t data[2];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_MDMCFG4, data, 2);
+
+ uint16_t cfg = data[0] & CC1101_REG_RW_MDMCFG4_MASK;
cfg = cfg << 8;
- cfg |= cc1101_spi_read_register(CC1101_REG_RW_MDMCFG3) & CC1101_REG_RW_MDMCFG3_MASK;
+ cfg |= data[1] & CC1101_REG_RW_MDMCFG3_MASK;
return cfg;
}
@@ -497,7 +512,10 @@ void cc1101_set_deviatn(uint8_t dev)
uint32_t cc1101_get_mcsm(void)
{
- uint32_t cfg = cc1101_spi_read_register(CC1101_REG_RW_MCSM2) & CC1101_REG_RW_MCSM2_MASK;
+ uint8_t data[3];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_MCSM2, data, 3);
+
+ uint32_t cfg = data[0] & CC1101_REG_RW_MCSM2_MASK;
cfg = cfg << 8;
cfg |= cc1101_spi_read_register(CC1101_REG_RW_MCSM1) & CC1101_REG_RW_MCSM1_MASK;
cfg = cfg << 8;
@@ -537,11 +555,14 @@ void cc1101_set_bscfg(uint8_t cfg)
uint32_t cc1101_get_agcctrl(void)
{
- uint32_t ctrl = cc1101_spi_read_register(CC1101_REG_RW_AGCCTRL2) & CC1101_REG_RW_AGCCTRL2_MASK;
+ uint8_t data[3];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_AGCCTRL2, data, 3);
+
+ uint32_t ctrl = data[0] & CC1101_REG_RW_AGCCTRL2_MASK;
ctrl = ctrl << 8;
- ctrl |= cc1101_spi_read_register(CC1101_REG_RW_AGCCTRL1) & CC1101_REG_RW_AGCCTRL1_MASK;
+ ctrl |= data[1] & CC1101_REG_RW_AGCCTRL1_MASK;
ctrl = ctrl << 8;
- ctrl |= cc1101_spi_read_register(CC1101_REG_RW_AGCCTRL0) & CC1101_REG_RW_AGCCTRL0_MASK;
+ ctrl |= data[2] & CC1101_REG_RW_AGCCTRL0_MASK;
return ctrl;
}
@@ -556,9 +577,12 @@ void cc1101_set_agcctrl(uint32_t ctrl)
uint16_t cc1101_get_worevt(void)
{
- uint16_t timeout = cc1101_spi_read_register(CC1101_REG_RW_WOREVT1) & CC1101_REG_RW_WOREVT1_MASK;
+ uint8_t data[2];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_WOREVT1, data, 2);
+
+ uint16_t timeout = data[0] & CC1101_REG_RW_WOREVT1_MASK;
timeout = timeout << 8;
- timeout |= cc1101_spi_read_register(CC1101_REG_RW_WOREVT0) & CC1101_REG_RW_WOREVT0_MASK;
+ timeout |= data[1] & CC1101_REG_RW_WOREVT0_MASK;
return timeout;
}
@@ -582,9 +606,12 @@ void cc1101_set_worctrl(uint8_t ctrl)
uint16_t cc1101_get_frend(void)
{
- uint16_t cfg = cc1101_spi_read_register(CC1101_REG_RW_FREND1) & CC1101_REG_RW_FREND1_MASK;
+ uint8_t data[2];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_FREND1, data, 2);
+
+ uint16_t cfg = data[0] & CC1101_REG_RW_FREND1_MASK;
cfg = cfg << 8;
- cfg |= cc1101_spi_read_register(CC1101_REG_RW_FREND0) & CC1101_REG_RW_FREND0_MASK;
+ cfg |= data[1] & CC1101_REG_RW_FREND0_MASK;
return cfg;
}
@@ -597,13 +624,16 @@ void cc1101_set_frend(uint16_t cfg)
uint32_t cc1101_get_fscal(void)
{
- uint32_t cal = cc1101_spi_read_register(CC1101_REG_RW_FSCAL3) & CC1101_REG_RW_FSCAL3_MASK;
+ uint8_t data[4];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_FSCAL3, data, 4);
+
+ uint32_t cal = data[0] & CC1101_REG_RW_FSCAL3_MASK;
cal = cal << 8;
- cal |= cc1101_spi_read_register(CC1101_REG_RW_FSCAL2) & CC1101_REG_RW_FSCAL2_MASK;
+ cal |= data[1] & CC1101_REG_RW_FSCAL2_MASK;
cal = cal << 8;
- cal |= cc1101_spi_read_register(CC1101_REG_RW_FSCAL1) & CC1101_REG_RW_FSCAL1_MASK;
+ cal |= data[2] & CC1101_REG_RW_FSCAL1_MASK;
cal = cal << 8;
- cal |= cc1101_spi_read_register(CC1101_REG_RW_FSCAL0) & CC1101_REG_RW_FSCAL0_MASK;
+ cal |= data[3] & CC1101_REG_RW_FSCAL0_MASK;
return cal;
}
@@ -620,9 +650,12 @@ void cc1101_set_fscal(uint32_t cal)
uint16_t cc1101_get_rcctrl(void)
{
- uint16_t ctrl = cc1101_spi_read_register(CC1101_REG_RW_RCCTRL1) & CC1101_REG_RW_RCCTRL1_MASK;
+ uint8_t data[2];
+ cc1101_spi_read_register_burst(CC1101_REG_RW_RCCTRL1, data, 2);
+
+ uint16_t ctrl = data[0] & CC1101_REG_RW_RCCTRL1_MASK;
ctrl = ctrl << 8;
- ctrl |= cc1101_spi_read_register(CC1101_REG_RW_RCCTRL0) & CC1101_REG_RW_RCCTRL0_MASK;
+ ctrl |= data[1] & CC1101_REG_RW_RCCTRL0_MASK;
return ctrl;
}
@@ -727,9 +760,12 @@ uint8_t cc1101_get_marcstate(void)
uint16_t cc1101_get_wortime(void)
{
- uint16_t w = cc1101_spi_read_register(CC1101_REG_RO_WORTIME1) & CC1101_REG_RO_WORTIME1_MASK;
+ uint8_t data[2];
+ cc1101_spi_read_register_burst(CC1101_REG_RO_WORTIME1, data, 2);
+
+ uint16_t w = data[0] & CC1101_REG_RO_WORTIME1_MASK;
w = w << 8;
- w |= cc1101_spi_read_register(CC1101_REG_RO_WORTIME0) & CC1101_REG_RO_WORTIME0_MASK;
+ w |= data[1] & CC1101_REG_RO_WORTIME0_MASK;
return w;
}